MT48LC16M8A2FB-75 Micron Semiconductor Products, MT48LC16M8A2FB-75 Datasheet

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MT48LC16M8A2FB-75

Manufacturer Part Number
MT48LC16M8A2FB-75
Description
Manufacturer
Micron Semiconductor Products
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC16M8A2FB-75 IT:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48LC16M8A2FB-75:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
• Configurations
• WRITE Recovery (
• Package/Pinout
• Timing (Cycle Time)
• Self Refresh
• Operating Temperature Range
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
SYNCHRONOUS
DRAM
edge of system clock
changed every clock cycle
PRECHARGE, and Auto Refresh Modes
t
Plastic Package – OCPL
54-pin TSOP II (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
Standard
Low power
Commercial (0
Industrial (-40
WR = “2 CLK”
32 Meg x 4
16 Meg x 8
8 Meg x 16 (2 Meg x 16 x 4 banks)
2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatability.
6. See page 59 for FBGA Device Marking Table.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MT48LC16M8A2TG-7E
(8 Meg x 4
(4 Meg x 8
1
o
o
C to +85
C to +70
Part Number Example:
t
WR)
2
o
o
C)
C)
x 4 banks)
x 4 banks)
MARKING
-8E
32M4
16M8
8M16
None
None
FC
FB
-75
-7E
IT
TG
A2
L
3,4,5
3,6
3,6
3
1
KEY TIMING PARAMETERS
*CL = CAS (READ) latency
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
Note: The # symbol indicates signal is active LOW. A dash (–)
GRADE FREQUENCY CL = 2* CL = 3*
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
SPEED
-8E
-8E
DQ0
DQ1
x4
-7E
-7E
-75
-75
NC
NC
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3 ,4,5
3,4,5
www.micron.com/dramds
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ0
DQ1
DQ2
DQ3
indicates x8 and x4 pin function is same as x16 pin function.
x8
NC
NC
NC
NC
NC
PIN ASSIGNMENT (Top View)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DQML
x16
V
V
CAS#
RAS#
VssQ
VssQ
WE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BA0
BA1
DD
DD
A10
V
V
V
CS#
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
A0
A1
A2
A3
DD
DD
DD
CLOCK
Q
Q
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
2K (A0–A9, A11)
32 Meg x 4
4K (A0–A11)
4 (BA0, BA1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54-Pin TSOP
4K
128Mb: x4, x8, x16
ACCESS TIME
5.4ns
6ns
6ns
16 Meg x 8
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
5.4ns
5.4ns
6ns
4K
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
©2001, Micron Technology, Inc.
SETUP
TIME
1.5ns
1.5ns
1.5ns
1.5ns
SDRAM
x16
Vss
DQ15
VssQ
DQ14
DQ13
V
DQ12
DQ11
VssQ
DQ10
DQ9
V
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
2ns
2ns
DD
DD
Q
Q
8 Meg x 16
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
x8
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
4K
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
1ns
1ns
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
x4
-

Related parts for MT48LC16M8A2FB-75

MT48LC16M8A2FB-75 Summary of contents

Page 1

SYNCHRONOUS DRAM FEATURES • PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable ...

Page 2

Meg 16mm and 11 x 13mm Vss NC B VssQ DQ3 VssQ DQ2 ...

Page 3

... Meg x 4 MT48LC32M4A2FC* 32 Meg x 4 MT48LC32M4A2FB* 32 Meg x 4 MT48LC16M8A2TG 16 Meg x 8 MT48LC16M8A2FC* 16 Meg x 8 MT48LC16M8A2FB* 16 Meg x 8 MT48LC8M16A2TG 8 Meg x 16 *See page 59 for FBGA Device Marking Table. GENERAL DESCRIPTION ® The Micron 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits ...

Page 4

TABLE OF CONTENTS Functional Block Diagram – 32 Meg x 4 ................ Functional Block Diagram – 16 Meg x 8 ................ Functional Block Diagram – 8 Meg x 16 ................ Pin Descriptions ..................................................... Functional Description ......................................... Initialization ...................................................... Register Definition ...

Page 5

CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 11 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 FUNCTIONAL BLOCK DIAGRAM 32 Meg x 4 SDRAM ...

Page 6

CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 10 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 FUNCTIONAL BLOCK DIAGRAM 16 Meg x 8 SDRAM ...

Page 7

CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 9 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 FUNCTIONAL BLOCK DIAGRAM 8 Meg x 16 SDRAM ...

Page 8

PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL 38 CLK 37 CKE 19 CS# 16, 17, 18 WE#, CAS#, RAS# 39 x4, x8: DQM 15, 39 x16: DQML, DQMH 20, 21 BA0, BA1 23-26, 29-34, 22, 35 A0-A11 ...

Page 9

FUNCTIONAL DESCRIPTION In general, the 128Mb SDRAMs (8 Meg banks, 4 Meg banks and 2 Meg banks) are quad- bank DRAMs that operate at 3.3V and include a ...

Page 10

Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...

Page 11

CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks ...

Page 12

Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note: 1) NAME (FUNCTION) COMMAND INHIBIT ...

Page 13

COMMAND INHIBIT The COMMAND INHIBIT function prevents new com- mands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effec- tively deselected. Operations already in progress are not affected. NO OPERATION (NOP) ...

Page 14

AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent must be issued each time a refresh is required. All active banks ...

Page 15

Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE com- mand, which selects both the bank and ...

Page 16

READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto ...

Page 17

This is shown in Figure 7 for CAS latencies of two and three; data element either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a ...

Page 18

T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ NOTE: Each READ command may be to any bank. DQM is LOW. 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. ...

Page 19

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may ...

Page 20

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. ...

Page 21

PRECHARGE command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page ...

Page 22

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto ...

Page 23

Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, ...

Page 24

Fixed-length or full-page WRITE bursts can be trun- cated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coinci- dent with the BURST TERMINATE command will be ignored. The last data written (provided that DQM ...

Page 25

CLOCK SUSPEND The clock suspend mode occurs when a column ac- cess/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “freezing” the synchronous logic. For each positive clock edge ...

Page 26

CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. ...

Page 27

WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appear- ing CAS latency later. The PRECHARGE to bank ...

Page 28

TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...

Page 29

TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L L ...

Page 30

NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...

Page 31

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row L ...

Page 32

NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the ...

Page 33

ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V ........................................ -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V ........................................ -1V to +4.6V SS Operating Temperature, T (commercial) ........................................ 0°C ...

Page 34

CAPACITANCE (Note: 2; notes appear on page 36) PARAMETER - TSOP “TG” Package Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs PARAMETER - FBGA “FB” Package Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output ...

Page 35

AC FUNCTIONAL CHARACTERISTICS (Notes 11; notes appear on page 36) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to ...

Page 36

NOTES 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V dependent on output loading and cycle rates. DD Specified ...

Page 37

INITIALIZE AND LOAD MODE REGISTER CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ( ) ) COMMAND ...

Page 38

CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all ...

Page 39

CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM / DQML, DQMH A0-A9, A11 COLUMN m ...

Page 40

T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all ...

Page 41

T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all ...

Page 42

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 DISABLE AUTO PRECHARGE ...

Page 43

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 ...

Page 44

SINGLE READ – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...

Page 45

SINGLE READ – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...

Page 46

ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW ...

Page 47

CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0-A9, A11 ROW ...

Page 48

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...

Page 49

WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH A0-A9, A11 COLUMN m 3 ROW ...

Page 50

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0-A9, A11 ROW ENABLE ...

Page 51

SINGLE WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...

Page 52

SINGLE WRITE – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM / DQML, DQMH A0-A9, A11 ROW ...

Page 53

ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0-A9, A11 ROW t ...

Page 54

CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...

Page 55

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 BA0, BA1 ...

Page 56

TYP .45 .30 PIN #1 ID .75 (2X) 1.00 (2X) NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per ...

Page 57

SEATING PLANE 0.10 ∅0.45 ± 0.05 8.00 ±0.05 16.00 ±0.10 5.60 ±0.05 2.80 ±0.05 NOTE: 1. All dimensions in millimeters. 2. Recommended Pad size for PCB is 0.33mm±0.025mm. 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 FBGA ...

Page 58

SEATING PLANE 0.10 ∅ 0.45 ±0.05 6.50 ±0.05 13.00 ±0.10 5.60 ±0.05 2.80 ±0.05 NOTE: 1. All dimensions in millimeters. 2. Recommended Pad size for PCB is 0.33mm±0.025mm. 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 FBGA ...

Page 59

... MT48LC32M4A2FB-7E 32 Meg x 4 MT48LC16M8A2FC-75 16 Meg x 8 MT48LC16M8A2FC-7E 16 Meg x 8 MT48LC16M8A2FB-75 16 Meg x 8 MT48LC16M8A2FB-7E 16 Meg x 8 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. ...

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