MT28F640J3RG-11ET Micron Semiconductor Products, MT28F640J3RG-11ET Datasheet
MT28F640J3RG-11ET
Related parts for MT28F640J3RG-11ET
MT28F640J3RG-11ET Summary of contents
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... FBGA (1.0mm pitch) -12 -11 *Contact factory for availability of the MT28F320J3 and None MT28F640J3 PRODUCTION DATA SHEET SPECIFICATIONS. 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ‡ , MT28F640J3, ‡ 56-Pin TSOP Type I 64-Ball FBGA None Part Number Example: MT28F640J3RG-12 ET ©2002, Micron Technology, Inc. ...
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GENERAL DESCRIPTION The MT28F128J3 is a nonvolatile, electrically block- erasable (Flash), programmable memory containing 134,217,728 bits organized as 16,777,218 bytes (8 bits) or 8,388,608 words (16 bits). This 128Mb device is orga- nized as one hundred twenty-eight 128KB erase blocks. ...
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DEVICE MARKING Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a Cross Reference for Abbreviated Device Marks PART NUMBER MT28F320J3FS-11 MT28F320J3FS-11 ...
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I/O Control Logic A0–A23 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN I/O Control Logic A0–A22 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN ...
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I/O Control Logic A0–A21 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 FUNCTIONAL BLOCK DIAGRAM (32Mb) Addr. Buffer/ Latch Addr. Power ...
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PIN/BALL DESCRIPTIONS 56-PIN TSOP 64-BALL FBGA NUMBERS NUMBERS B4, B8 32, 28, 27, G2, A1, B1, C1, 26, 25, 24, 23, D1, D2, A2, C2, 22, 20, 19, 18, A3, ...
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PIN/BALL DESCRIPTIONS (continued) 56-PIN TSOP 64-BALL FBGA NUMBERS NUMBERS H3, A6 21, 42, 48 B2, H4 – B6, C6, D5, D6, E6, F6, F7, H2 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. ...
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MEMORY ARCHITECTURE The MT28F128J3, MT28F640J3, and MT28F320J3 memory array architecture is divided into one hun- dred twenty-eight, sixty-four, or thirty-two 128KB blocks, respectively (see Figure 1). The internal archi- tecture allows greater flexibility when updating data because individual code portions ...
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After RP# goes to logic HIGH (V t after RS, another command can be written important to ...
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MODE RP# Read Array V IH Output Disable V IH Standby V IH Reset/Power-Down V IL Mode Read Identifier Codes V IH Read Query V IH Read Status (ISM off Read Status (ISM on DQ7 DQ15–DQ8 ...
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COMMAND DEFINITIONS When the V voltage is less than V PEN operations from the status register, query, identifier codes, or blocks are enabled. Placing V ables BLOCK ERASE, PROGRAM, and LOCK BIT CON- Micron Q-Flash Memory Command Set Definitions COMMAND ...
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NOTE: 1. Commands other than those shown in Table 4 are reserved for future device implementations and should not be used. 2. The SCS is also referred to as the extended command set. 3. Bus operations are defined in Table ...
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READ ARRAY COMMAND The device defaults to read array mode upon initial device power-up and after exiting reset/power-down mode. The read configuration register defaults to asyn- chronous read page mode. Until another command is written, the READ ARRAY command also ...
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QUERY STRUCTURE OVERVIEW The QUERY command makes the Flash component display the CFI query structure or data base. The struc- ture subsections and address locations are outlined in Table 7. Example of Query Structure Output of a x16- and x8-Capable ...
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CFI QUERY IDENTIFICATION STRING The CFI query identification string verifies whether the component supports the CFI specification. Addi- OFFSET LENGTH DESCRIPTION 1 (BA+2)h 1 Block Lock Status Register BSR0 Block Lock Status 0 = Unlocked 1 = Locked BSR1–7 Reserved ...
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SYSTEM INTERFACE INFORMATION Table 10 provides useful information about opti- mizing system interface software. OFFSET LENGTH DESCRIPTION 1Bh 1 V logic supply minimum program/erase voltage CC Bits 0–3 BCD 100mV Bits 4–7 BCD volts 1Ch 1 V logic supply maximum ...
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DEVICE GEOMETRY DEFINITION Tables 11a and 11b provide important details about the device geometry. OFFSET LENGTH DESCRIPTION 27h 1 “n” such that device size = 2 28h 2 Flash device interface: x8 async, x16 async, x8/x16 async; 28:00 29:00, 28:01 ...
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PRIMARY VENDOR-SPECIFIC EXTENDED QUERY TABLE Table 12 includes information about optional Flash features and commands and other similar infor- mation. Primary Vendor-Specific Extended Query 1 OFFSET DESCRIPTION P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS) (P+0)h Primary extended query table ...
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OFFSET DESCRIPTION P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS) (P+E)h Number of protection register fields in JEDEC ID space. “00h” indicates that 256 protection bytes are available. (P+F)h Protection Field 1: Protection Description (P+10)h This field describes user-available, ...
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READ IDENTIFIER CODES COMMAND Writing the READ IDENTIFIER CODES command initiates the IDENTIFIER CODE operation. Following the writing of the command, READ cycles from ad- dresses shown in Figure 2 retrieve the manufacturer, device, and block lock configuration codes (see ...
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ISMS ESS 7 6 HIGH-Z WHEN STATUS REGISTER BITS BUSY? No SR7 = WRITE STATE MACHINE STATUS (ISMS Ready 0 = Busy Yes SR6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase ...
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Extended Status Register Definitions (XSR) WBS 7 HIGH-Z WHEN STATUS REGISTER BITS BUSY? No XSR7 = WRITE BUFFER STATUS (WBS Write Buffer Available 0 = Write Buffer Not Available Yes XSR6–XSR0 = RESERVED FOR FUTURE ENHANCEMENTS CLEAR STATUS ...
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To resume the suspended erase, the user must wait for the programming operation to complete be- fore issuing the BLOCK ERASE RESUME command. While block erase is suspended, the only other valid ...
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PROGRAM SUSPEND command requests that the ISM suspend the program sequence at a predeter- mined point in the algorithm. When the PROGRAM SUSPEND command is written, the device continues to output status register data when read. Polling status ...
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DQ7 DQ6 DQ1–DQ0 = STS Configuration Codes 00 = Default, RY/BY# level mode (device ready) indication 01 = Pulse on Erase Complete 10 = Pulse on Program Complete 11 = Pulse on Erase or Program Complete NOTE invalid ...
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LOCK BITS operation is attempted when V SR3 and SR5 are set to “1.” CLEAR BLOCK LOCK BITS operation is aborted due to V out of valid range, block lock bit values are left in an undetermined state. ...
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Word-Wide Protection Register Addressing WORD USE LOCK Both 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Byte-Wide Protection Register Addressing BYTE USE LOCK Both 0 Factory 1 Factory 2 Factory 3 Factory ...
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Figure 4 WRITE-to-BUFFER Flowchart Start Set Timeout Issue No WRITE-to-BUFFER Command E8h, Block Address Read Extended Status Register WRITE-to- 0 XSR7 = BUFFER Timeout? 1 Write Word or Byte Count N, Block Address Write Buffer Data, Start Address X = ...
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Figure 5 Byte/Word Program Flowchart Start Write 40h, Address Write Data and Address Read Status Register 0 SR7 = 1 Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (see above) 1 Voltage ...
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Figure 6 PROGRAM SUSPEND/RESUME Flowchart Start Write B0h Read Status Register 0 SR7 = 1 0 SR2 = 1 Write FFh Read Data Array 1 No Done Reading Yes Write D0h Programming Resumed 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – ...
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Figure 7 BLOCK ERASE Flowchart Start Issue Single BLOCK ERASE Command 20h, Block Address Write Confirm D0h Block Address Read Status Register No SR7 = Suspend Erase 1 Full Status Check if Desired Erase Flash Block(s) Complete 128Mb, 64Mb, 32Mb ...
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Figure 8 BLOCK ERASE SUSPEND/RESUME Flowchart Start Write B0h Read Status Register 0 SR7 = 1 0 SR6 = 1 Read Read or Program Program? Read Array Program No Data Loop Done? Yes Write D0h BLOCK ERASE Resumed 128Mb, 64Mb, ...
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Figure 9 SET BLOCK LOCK BITS Flowchart Start Write 60h, Block Address Write 01h, Block Address Read Status Register 0 SR7 = 1 Full Status Check if Desired SET BLOCK LOCK BITs Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Figure 10 CLEAR BLOCK LOCK BITS Flowchart Start Write 60h Write D0h Read Status Register 0 SR7 = 1 Full Status Check if Desired CLEAR BLOCK LOCK BITS Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (see above) 1 ...
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Figure 11 PROTECTION REGISTER PROGRAMMING Flowchart Start Write C0h (Protection Register Program Setup) Write Protect Register Address/Data Read Status Register No SR7 = 1 Yes Full Status Check if Desired PROGRAM Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...
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DESIGN CONSIDERATIONS FIVE-LINE OUTPUT CONTROL Micron provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory con- nections in large memory arrays. This control provides the lowest possible memory power dissipation and en- sures that data ...
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REDUCING OVERSHOOTS AND UNDER- SHOOTS WHEN USING BUFFERS OR TRANSCEIVERS Overshoots and undershoots can sometimes cause input signals to exceed Flash memory specifications as faster, high-drive devices such as transceivers or buff- ers drive input signals to Flash memory devices. ...
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ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Expanded ................................... –40ºC to +85ºC Storage Temperature ........................... –65ºC to +125ºC For +2.7V to +3.6V CC Voltage On Any Pin ........................ –2.0V to +5.0V** For +4.5V to +5.5V ...
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... NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). 2. Sampled, not 100% tested. 3. Includes STS. 4. MT28F320J3RG-11 F and MT28F640J3RG-12 F only. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ T ...
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CAPACITANCE (T = +25º MHz) A PARAMETER/CONDITION Input Capacitance Output Capacitance BYTE# All other Pins RECOMMENDED DC ELECTRICAL CHARACTERISTICS Commercial Temperature (0ºC ≤ T DESCRIPTION V Standby CMOS Inputs Current V Power-Down CC Current V ...
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RECOMMENDED DC ELECTRICAL CHARACTERISTICS (continued) Commercial Temperature (0ºC ≤ T DESCRIPTION V Program or Set CC Lock Bits Current V Block Erase or Clear CC Block Lock Bits Current V Program Suspend or CC Block Erase Suspend Current V Lockout ...
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Transient Input/Output Reference Waveform for Input V 0.0 NOTE: AC test inputs are driven (50 Q). Input rise and fall times (10% to 90%) < 5ns. CC Transient Equivalent Testing Load Circuit ...
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AC CHARACTERISTICS – READ-ONLY OPERATIONS (Notes 4); Commercial Temperature (0ºC ≤ T PARAMETER READ/WRITE Cycle Time Address to Output Delay CEx to Output Delay OE# to Non-Array Output Delay OE# to Array Output Delay RP# HIGH to Output ...
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PAGE MODE AND STANDARD WORD/BYTE READ OPERATIONS V IH ADDRESSES V (A22–A3 ADDRESSES V (A2–A0 Disabled IH CEx V Enabled OE WE DQ0–DQ15 V ...
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AC CHARACTERISTICS – WRITE OPERATIONS (Notes 3); Commercial Temperature (0ºC ≤ CHARACTERISTICS PARAMETER RP# High Recovery to WE# (CEx) Going LOW CEx (WE#) LOW to WE# (CEx) Going LOW Write Pulse Width Data Setup to WE# ...
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BLOCK ERASE, PROGRAM, AND LOCK BIT CONFIGURATION PERFORMANCE (Notes 3); Commercial Temperature (0ºC ≤ T CHARACTERISTICS PARAMETER Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte/Word Program Time (Using WORD/BYTE PROGRAM Command) Block Program Time ...
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Note Addresses Disabled V CEx (WE#) IL Enabled OE Disabled IH WE# (CEx) V Enabled DQ0–DQ15 STS V OL ...
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V IH Addresses Disabled V CEx (WE#) IL Enabled Disabled IH WE# (CEx) V Enabled DQ0–DQ15 STS RP# V ...
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RESET SPECIFICATIONS (Note: 1); Commercial Temperature (0ºC ≤ T CHARACTERISTICS PARAMETER RP# Pulse Low Time (If RP# is tied this specification is not applicable) CC RP# HIGH to Reset during Block Erase, Program, or Lock Bit Configuration ...
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PIN #1 INDEX +0.03 0.15 -0.02 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ...
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SEATING PLANE C 0.08 C BALL A8 64X ∅0.45 1.00 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.40 7.00 ±0.05 3.50 ±0.05 3.50 ±0.05 10.00 ±0.10 NOTE: 1. All dimensions ...
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REVISION HISTORY Rev. 6 ......................................................................................................................................................................................... 8/02 • Added commercial temperature range • Updated Configuration Coding Definitions table • Removed 3.0V–3. voltage range option • Updated AOA, ODC, LKO PENLK • Added ...