74LS195 ON Semiconductor, 74LS195 Datasheet

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74LS195

Manufacturer Part Number
74LS195
Description
LOW POWER SCHOTTKY
Manufacturer
ON Semiconductor
Datasheet

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74LS195
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MIT
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74LS195AB1
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74LS195APC
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SN74LS195A
Universal 4-Bit
Shift Register
typical shift frequencies of 39 MHz. It is useful for a wide variety of
register and counting applications. It utilizes the Schottky diode
clamped process to achieve high speeds and is fully compatible with
all ON Semiconductor TTL products.
GUARANTEED OPERATING RANGES
December, 1999 – Rev. 6
Symbol
The SN74LS195A is a high speed 4-Bit Shift Register offering
Typical Shift Right Frequency of 39 MHz
Asynchronous Master Reset
J, K Inputs to First Stage
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
Semiconductor Components Industries, LLC, 1999
V
I
I
T
OH
OL
CC
A
Supply Voltage
Operating Ambient
Output Current – High
Output Current – Low
Temperature Range
Parameter
4.75
Min
0
Typ
5.0
25
Max
5.25
– 0.4
8.0
70
1
Unit
mA
mA
V
C
SN74LS195AN
SN74LS195AD
Device
ORDERING INFORMATION
16
http://onsemi.com
SCHOTTKY
16
1
16 Pin DIP
POWER
CASE 751B
Package
CASE 648
N SUFFIX
D SUFFIX
PLASTIC
16 Pin
LOW
SOIC
Publication Order Number:
1
2500/Tape & Reel
2000 Units/Box
SN74LS195A/D
Shipping

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74LS195 Summary of contents

Page 1

... SN74LS195A Universal 4-Bit Shift Register The SN74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products ...

Page 2

... SN74LS195A CONNECTION DIAGRAM DIP (TOP VIEW PIN NAMES PE Parallel Enable (Active LOW) Input P – P Parallel Data Inputs First Stage J (Active HIGH) Input K First Stage K (Active LOW) Input ...

Page 3

... I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition HIGH voltage level one set-up time prior to the LOW to HIGH clock transition Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW HIGH clock transition. SN74LS195A LOGIC DIAGRAM ...

Page 4

... PE Setup Time s t Data Setup Time s t Recovery Time rec t PE Release Time rel t Data Hold Time h SN74LS195A (unless otherwise specified) Limits Min Typ Max Unit Guaranteed Input HIGH Voltage for 2.0 V All Inputs 0.8 Guaranteed Input LOW Voltage for V All Inputs – ...

Page 5

... Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time SN74LS195A continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (t ...

Page 6

... SEATING –T– PLANE 0.25 (0.010 SN74LS195A N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 7

... G K –T– SEATING PLANE 0.25 (0.010 SN74LS195A D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE 0.25 (0.010 http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 8

... Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5487–8345 Email: r14153@onsemi.com Fax Response Line: 303–675–2167 800–344–3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 SN74LS195A/D ...

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