MT48LC16M16A2TG-7E Micron Semiconductor Products, MT48LC16M16A2TG-7E Datasheet
MT48LC16M16A2TG-7E
Specifications of MT48LC16M16A2TG-7E
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MT48LC16M16A2TG-7E Summary of contents
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... MHz 5.4ns -75 100 MHz 6ns Part Number Example: MT48LC16M16A2TG-75:D PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM_1.fm - Rev. L 10/07 EN Products and specifications discussed herein are subject to change by Micron without notice. www.micron.com Options • Configurations – 64 Meg x 4 (16 Meg banks) – 32 Meg Meg banks) – ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 64 Meg x 4 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 57: 54-Ball VFBGA “FG” Package, 8mm x 14mm (x16 ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... MT48LC64M4A2TG MT48LC64M4A2P MT48LC64M4A2FB MT48LC64M4A2BB MT48LC32M8A2TG MT48LC32M8A2P MT48LC32M8A2FB MT48LC32M8A2BB MT48LC16M16A2TG MT48LC16M16A2P MT48LC16M16A2FG MT48LC16M16A2BG Notes: 1. Actual FBGA part marking shown on pages 76 and 77. General Description The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...
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SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly ...
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Figure 2: 32 Meg x 8 SDRAM Functional Block Diagram CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER 10 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM_2.fm - Rev. L 10/07 EN ...
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Figure 3: 16 Meg x 16 SDRAM Functional Block Diagram CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER 9 PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM_2.fm - Rev. L 10/07 EN ...
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Pin/Ball Assignments and Descriptions Figure 4: 54-Pin TSOP Assignment (Top View DQ0 - NC DQ0 DQ1 - NC NC DQ2 - NC DQ1 DQ3 - ...
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Figure 5: 60-Ball FBGA Assignment (Top View) 64 Meg x 4 SDRAM 8mm x 16mm “FB” Vss NC B VssQ DQ3 VssQ ...
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Figure 6: 54-Ball FBGA Assignment (Top View Notes: 1. The balls at A4, A5, and A6 are absent from the physical package. They are included to illus- trate that rows 4, ...
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Table 4: 54-Pin TSOP Descriptions Pin Numbers Symbol 38 CLK 37 CKE 19 CS# 16, 17, 18 WE#, CAS#, RAS# 39 x4, x8: DQM 15, 39 x16: DQML, DQMH 20, 21 BA0, BA1 23–26, 29–34, 22, A0–A12 35 ...
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Table 5: 54-Ball and 60-Ball FBGA Descriptions 54-Ball 60-Ball FBGA FBGA Symbol F2 K2 CLK F3 L2 CKE G9 L8 CS# F7, F8, F9 J8, K7, J7 CAS#, RAS#, WE# E8 DQM, LDQM, UDQM G7, G8 M8, M7 ...
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Table 5: 54-Ball and 60-Ball FBGA Descriptions (continued) 54-Ball 60-Ball FBGA FBGA Symbol A1, A8, B1, NC B8, D1, D2, D7, D8, E1, E8, G1, G2, G7, G8, H1, H8, J1, K1, K8, L7 B1, B8, D2, NC D7, E1, ...
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INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. After the 100µs delay has been satisfied with at least ...
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Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of BL, a burst type, CL, an operating mode, and a write burst mode, as shown ...
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Figure 7: Mode Register Definition A12 12 Reserved Program BA1, BA0 = “0, 0” to ensure compatibility with future devices. Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access M8 M7 M6- Defined – – ...
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Burst Type Accesses within a given burst may be programmed either to be sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...
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If a READ command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one ...
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Table 7: CAS Latency Notes: 1. -6A speed grade supports latency of 3-3-3 cycles (CAS latency- 2. -7E speed grade supports latency of 2-2-2 cycles at 133 MHz (MAX). PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM_2.fm - Rev. L 10/07 EN Allowable Operating ...
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Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following “Operations” on page 25; these tables provide current state/next state information. Table 8: ...
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LOAD MODE REGISTER The mode register is loaded via inputs A0–A11 (A12 should be driven LOW.) See “Register Definition” on page 17. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable ...
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Auto Precharge Auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. ...
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AUTO REFRESH command every 7.81µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate ( SELF REFRESH The SELF REFRESH ...
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Figure 10: Activating a Specific Row in a Specific Bank CLK CKE CS# RAS# CAS# WE# A0–A12 BA0, BA1 Figure 11: Example: Meeting CLK COMMAND READs READ bursts are initiated with a READ command, as shown in Figure 12 on ...
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The new READ command should be issued x cycles before the clock ...
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Figure 13: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 256MSDRAM_2.fm - Rev. L 10/ CLK READ NOP NOP NOP BANK, ...
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Figure 14: Random READ Accesses CLK COMMAND ADDRESS CLK COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 10 on page 26 shows the case where the clock frequency ...
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Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a ...
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Figure 18: Terminating a READ Burst CLK COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 33. The starting column and bank addresses are provided ...
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Figure 19: WRITE Command A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 A11, A12: x8 A9, A11, A12: x16 Figure 20: WRITE Burst COMMAND ADDRESS Note DQM is LOW. Data for any WRITE burst may be truncated with ...
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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. After the READ command is registered, the data inputs will be ignored, ...
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The auto precharge mode requires a truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident ...
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PRECHARGE The PRECHARGE command (see Figure 25 on page 36) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified ...
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Figure 26: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is ...
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Figure 28: Clock Suspend During READ Burst INTERNAL CLOCK COMMAND ADDRESS Note: For this example greater, and DQM is LOW. Burst Read/Single Write Mode The burst read/single write mode is entered by programming ...
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Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after valid data WRITE to bank n will be ...
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Figure 31: WRITE With Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Notes: 1. DQM is LOW. Figure 32: WRITE With Auto Precharge Interrupted by a WRITE CLK COMMAND BANK n Internal ...
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Table 9: Truth Table 2 – CKE Notes 1–4 apply to the entire table CKE CKE Current State Power-down Self refresh Clock suspend L H Power-down Self refresh Clock suspend H L All banks ...
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Table 10: Truth Table 3 – Current State Bank n, Command to Bank n Notes 1–6 apply to the entire table; notes appear below and on page 43 Current State CS# RAS# Any Idle L L ...
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The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Accessing mode Precharging all: Starts with registration of a PRECHARGE ALL command ...
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Table 11: Truth Table 4 – Current State Bank n, Command to Bank m Notes 1–6 apply to the entire table; notes appear below and on page 45 Current State CS# RAS# Any Idle X X ...
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A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...
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Electrical Specifications Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 13: Temperature Limits Parameter Operating case temperature: Commercial Industrial Junction temperature: Commercial Industrial Ambient temperature: Commercial Industrial Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figure 33, Figure 34, and ...
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Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point Figure 35: Example Temperature Test Point Location, 60-Ball FBGA: Top View Test point PDF: ...
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Table 15: DC Electrical Characteristics and Operating Conditions Notes apply to the entire table; notes appear on page 54; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs ...
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Table 18: Capacitance Note 2 applies to the entire table; notes appear on page 54 Parameter – TSOP “TG” Package Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQs Parameter – FBGA “FB” and “FG” Package Input ...
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Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6A) Notes 11, 31 apply to the entire table; notes appear on page 54 Parameter Access time from CLK (positive edge) Address hold time Address setup time ...
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Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) Notes apply to the entire table; notes appear on page 54 Parameter Access time from CLK (positive edge ...
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Table 21: AC Functional Characteristics (-6A) Notes apply to the entire table; notes appear on page 54 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock ...
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Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used ...
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V IH cannot be greater than one-third of the cycle rate pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock ...
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Timing Diagrams Figure 36: Initialize and Load Mode Register CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH ( ( ) ) COMMAND ...
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Figure 37: Power-Down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMU A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active ...
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Figure 38: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM/ DQML, DQMU A0–A9, ...
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Figure 39: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMU A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ ...
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Figure 40: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMU A0–A9, A11,A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge ...
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Figure 41: Read – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, ROW A11, A12 ROW ...
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Figure 42: Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, ROW A11, A12 ENABLE ...
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Figure 43: Single Read – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, ROW A11,A12 ROW ...
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Figure 44: Single Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, A11 ROW ROW ...
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Figure 45: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0-A9, A11, A12 ROW ROW A10 ...
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Figure 46: Read – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU A0–A9, COLUMN m 2 ...
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Figure 47: Read – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, ROW A11, A12 ENABLE AUTO ...
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Figure 48: Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU A0–A9, COLUMN m 2 ROW ...
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Figure 49: Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU A0–A9, ROW COLUMN A11, A12 ...
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Figure 50: Single Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, A11 ROW ROW ...
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Figure 51: Single Write – With Auto Precharge CKS t CKH CKE t CMS t CMH NOP 2 COMMAND ACTIVE DQM/ DQML, DQMU A0–A9, ROW A11, A12 t ...
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Figure 52: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMU A0–A9, COLUMN m 3 ROW A11, ...
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Figure 53: Write – Full-Page Burst CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMU A0–A9, ROW A11, A12 ROW A10 ...
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Figure 54: Write – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM/ DQML, DQMU A0–A9, ROW A11, A12 ROW A10 t AS ...
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Package Dimensions Figure 55: 54-Pin Plastic TSOP (400 mil) PIN # 0. 1.00 10.16 ±0.08 11.76 ±0.20 +0.03 0.15 -0.02 Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold ...
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Figure 56: 60-Ball FBGA “FB” Package, 8mm x 16mm (x4, x8) 0.850 ±0.05 60X Ø 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE- REFLOW DIAMETER IS 0. 0.33 NSMD BALL PAD. BALL A8 8.00 ±0.05 16.00 ±0.10 ...
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Figure 57: 54-Ball VFBGA “FG” Package, 8mm x 14mm (x16) 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø0.42 BALL A9 6.40 3.20 ±0.05 3.20 ±0.05 ...