MT48LC4M16A2TG-75IT Micron Semiconductor Products, MT48LC4M16A2TG-75IT Datasheet
MT48LC4M16A2TG-75IT
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MT48LC4M16A2TG-75IT Summary of contents
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SYNCHRONOUS DRAM FEATURES • PC66-, PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • ...
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... SDRAM PART NUMBERS PART NUMBER ARCHITECTURE MT48LC16M4A2TG 16 Meg x 4 MT48LC8M8A2TG 8 Meg x 8 MT48LC4M16A2TG 4 Meg x 16 GENERAL DESCRIPTION ® The Micron 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory 67,108,864 bits internally configured as a quad- bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...
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TABLE OF CONTENTS Functional Block Diagram –16 Meg x 4 ............... Functional Block Diagram – 8 Meg x 8 ............... Functional Block Diagram – 4 Meg x 16 ............. Pin Descriptions ...................................................... Functional Description ......................................... Initialization ...................................................... Register Definition ............................................ ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 10 64Mb: x4, x8, x16 SDRAM 64MSDRAM_D.p65 – Rev. D; Pub. 5/01 FUNCTIONAL BLOCK DIAGRAM 16 Meg x 4 SDRAM ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 9 64Mb: x4, x8, x16 SDRAM 64MSDRAM_D.p65 – Rev. D; Pub. 5/01 FUNCTIONAL BLOCK DIAGRAM 8 Meg x 8 SDRAM ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 8 64Mb: x4, x8, x16 SDRAM 64MSDRAM_D.p65 – Rev. D; Pub. 5/01 FUNCTIONAL BLOCK DIAGRAM 4 Meg x 16 SDRAM ...
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PIN DESCRIPTIONS PIN NUMBERS SYMBOL 38 CLK 37 CKE 19 CS# 16, 17, 18 WE#, CAS#, RAS# 39 x4, x8: DQM 15, 39 x16: DQML, DQMH 20, 21 BA0, BA1 23-26, 29-34, 22, 35 A0-A11 ...
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FUNCTIONAL DESCRIPTION In general, the 64Mb SDRAMs (4 Meg banks, 2 Meg banks and 1 Meg banks) are quad- bank DRAMs which operate at 3.3V and include a ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is deter- mined ...
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CAS Latency The CAS latency is the delay, in clock cycles, be- tween the registration of a READ command and the availability of the first piece of output data. The la- tency can be set to two or three clocks. ...
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Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written de- scription of each command. Three additional Truth TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note : 1) NAME (FUNCTION) COMMAND INHIBIT ...
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, re- gardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The ...
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AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This com- mand is nonpersistent must be issued each time a refresh is required. All active ...
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Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be is- sued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the AC- TIVE command, which selects both the bank ...
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READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are pro- vided with the READ command, and auto precharge is either enabled or disabled for that burst access. If ...
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CAS latency minus one. This is shown in Figure 7 for CAS latencies of two and three; data element ...
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T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ NOTE: Each READ command may be to any bank. DQM is LOW. 64Mb: x4, x8, x16 SDRAM 64MSDRAM_D.p65 – Rev. D; Pub. ...
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Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turn- around limitations). The WRITE burst ...
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A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not acti- vated), and a full-page burst may be truncated with a PRECHARGE command to the same ...
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PRECHARGE command is that it requires that the com- mand and address buses be available at the appropri- ate time to issue the command; the advantage of the PRECHARGE command is that it can be used to trun- cate fixed-length ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...
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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed- length WRITE burst may be immediately followed by a subsequent READ command. Once the READ com- mand is registered, the data inputs ...
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Fixed-length or full-page WRITE bursts can be trun- cated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coin- cident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM ...
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CLOCK SUSPEND The clock suspend mode occurs when a column ac- cess/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “freezing” the synchronous logic. For each positive clock edge ...
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CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four ...
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WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appear- ing CAS latency later. The PRECHARGE to bank ...
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TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...
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TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS#CAS# WE# Any Idle ...
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...
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TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row L ...
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NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the ...
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ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V ............................................ -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V ............................................ -1V to +4.6V SS Operating Temperature, T (commercial) ...................................... ...
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CAPACITANCE (Note: 2; notes appear on page 35) PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 11; notes appear on page 35); V ...
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AC FUNCTIONAL CHARACTERISTICS (Notes 11; notes appear on page 35) V PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM ...
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NOTES 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V dependent on output loading and cycle rates. DD Specified ...
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INITIALIZE AND LOAD MODE REGISTER CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ( ) ) COMMAND ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge ...
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CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM / DQML, DQMH A0-A9, A11 COLUMN m ...
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T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM / DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge ...
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T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all active ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 DISABLE AUTO PRECHARGE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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SINGLE READ – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...
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SINGLE READ – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11, A12 ROW ROW ...
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ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0-A9, A11 ROW ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...
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WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 DISABLE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0-A9, A11 ROW ENABLE ...
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SINGLE WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...
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SINGLE WRITE – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM / DQML, DQMH A0-A9, A11 ROW ...
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ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0-A9, A11 ROW t ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 BA0, BA1 ...
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TYP .45 .30 PIN #1 ID .75 (2X) 1.00 (2X) NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per ...