ISPLSI1016E80LJ Lattice Semiconductor Corp., ISPLSI1016E80LJ Datasheet

ISPLSI1016E80LJ

Manufacturer Part Number

ISPLSI1016E80LJ

Description

ISPLSI1016E80LJHigh-Density Programmable Logic

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI1016E80LJI.pdf (15 pages)

Specifications of ISPLSI1016E80LJ

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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH-PERFORMANCE E

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

• OFFERS THE EASE OF USE AND FAST SYSTEM

• pLSI/ispLSI DEVELOPMENT TOOLS

Features

— 2000 PLD Gates

— 32 I/O Pins, Four Dedicated Inputs

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Device for Faster Prototyping

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

ispDS+™ Software

pDS

Machines, Address Decoders, etc.

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

— Easy to Use PC Windows™ Interface

— Boolean Logic Compiler

— Manual Partitioning

— Automatic Place and Route

— Static Timing Table

— Industry Standard, Third-Party Design

— Schematic Capture, State Machine, HDL

— Automatic Partitioning and Place and Route

— Comprehensive Logic and Timing Simulation

— PC and Workstation Platforms

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

Environments

Software

CMOS

TECHNOLOGY

ispLSI

The ispLSI and pLSI 1016E are High-Density

Programmable Logic Devices containing 96 Registers,

32 Universal I/O pins, four Dedicated Input pins, three

Dedicated Clock Input pins, one Global OE input pin and

a Global Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 1016E features 5-Volt in-system programming

and in-system diagnostic capabilities. The ispLSI 1016E

offers non-volatile “on-the-fly” reprogrammability of the

logic, as well as the interconnect to provide truly

reconfigurable systems. It is architecturally and

parametrically compatible to the pLSI 1016E device, but

multiplexes four input pins to control in-system

programming. A functional superset of the ispLSI and

pLSI 1016 architecture, the ispLSI and pLSI 1016E

devices add a new global output enable pin.

The basic unit of logic on the ispLSI and pLSI 1016E

devices is the Generic Logic Block (GLB). The GLBs are

labeled A0, A1...B7 (see figure 1). There are a total of 16

GLBs in the ispLSI and pLSI 1016E devices. Each GLB

has 18 inputs, a programmable AND/OR/Exclusive OR

array, and four outputs which can be configured to be

either combinatorial or registered. Inputs to the GLB

come from the GRP and dedicated inputs. All of the GLB

outputs are brought back into the GRP so that they can

be connected to the inputs of any other GLB on the

device.

Functional Block Diagram

Description

High-Density Programmable Logic

and pLSI

Global Routing Pool (GRP)

Logic

Array

D Q

1996 ISP Encyclopedia

GLB

1016E

February 1997

CLK

0139C1-isp

Related parts for ISPLSI1016E80LJ

ISPLSI1016E80LJ Summary of contents

Page 1

... Comprehensive Logic and Timing Simulation — PC and Workstation Platforms Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 2

Functional Block Diagram Figure 1. ispLSI and pLSI 1016E Functional Block Diagram Generic Logic Blocks (GLBs) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 ...

Page 3

Absolute Maximum Ratings Supply Voltage V ................................. -0.5 to +7.0V CC Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...

Page 4

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure 2) TEST ...

Page 5

External Timing Parameters 4 TEST 2 PARAMETER # COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 Data Prop. Delay, Worst Case Path pd2 Clk. Frequency with Int. Feedback max f ...

Page 6

Internal Timing Parameters 2 PARAMETER # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t 24 I/O Register Setup Time before Clock iosu t 25 I/O Register Hold Time after Clock ioh t 26 I/O ...

Page 7

Internal Timing Parameters 2 PARAMETER # Outputs t 49 Output Buffer Delay Output Slew Limited Delay Adder I/O Cell OE to Output Enabled oen t 52 I/O Cell OE to Output Disabled odis t ...

Page 8

Timing Model I/O Cell Ded. In #28 I/O Reg Bypass I/O Pin #22 (Input) Input Loading Register Q D RST #29, 31, 32 #59 # Reset Distribution Y1,2 Y0 GOE ...

Page 9

Maximum GRP Delay vs GLB Loads Power Consumption Power Consumption in the ispLSI and pLSI 1016E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device ...

Page 10

In-System Programmability The ispLSI devices are the in-system programmable versions of the Lattice Semiconductor High-Density Pro- grammable Large Scale Integration (pLSI) devices. By integrating all the high voltage programming circuitry on- chip, programming can be accomplished by simply shifting data ...

Page 11

Shift Register Layout 79... Data In (SDI) 159... Note: A logic “1” in the Address Shift Register bit position enables the row for programming or verification. A logic “0” disables it. Specifications ispLSI and ...

Page 12

Pin Description PLCC NAME PIN NUMBERS I I/O 3 15, 16, 17, 18, 13, I I/O 7 19, 20, 21, 22, I I/O 11 25, 26, 27, 28, 19, 23, I I/O ...

Page 13

Pin Configurations ispLSI and pLSI 1016E 44-pin PLCC Pinout Diagram * Pins have dual function capability for ispLSI 1016E only (except pin 13, which is ispEN only). ** Pins have dual function capability which is software selectable. ispLSI 1016E 44-pin ...

Page 14

Part Number Description (is)pLSI Device Family ispLSI pLSI Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax MHz fmax ispLSI and pLSI 1016E Ordering Information FAMILY fmax (MHz) tpd (ns) 125 125 100 ...

Page 15

Copyright © 1997 Lattice Semiconductor Corporation CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ...

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