21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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Table 7-4. SA-110 Control and Status Registers
Register
Timer2Clear
Reserved
Timer3Load
Timer3Value
Timer3Control
Timer3Clear
Reserved
Timer4Load
Timer4Value
Timer4Control
Timer4Clear
Reserved
a.
This register is accessed by two different addresses.
7.3.1
DMA Channel n Byte Count Register—Offset 80h/A0h
The DMA channel n byte count register (n = 1 or 2) contains the following fields.
Dword Bit
Name
23:0
Byte count
29:24
Channel interburst
delay
30
Channel transfer
direction
31
End of chain
21285 Core Logic for SA-110 Datasheet
(Sheet 3 of 3)
Offset
32Ch
330h to 33Ch
340h
344h
348h
34Ch
350h to 35Ch
360h
364h
368h
36Ch
370h to 7FCh
R/W
Description
R/W
Indicates the number of bytes to be transferred. It is
updated internally after each read as the DMA operation
progresses.
Reset value: Undefined.
R/W
Indicates the number of counts of the prescaled value (see
Section 7.3.5
bits [9:8]) that the channel will wait before
attempting another PCI burst.
Reset value: Undefined.
R/W
When 0: PCI to SDRAM.
When 1: SDRAM to PCI.
Reset value: Undefined.
R/W
When 0: Indicates that more descriptor list entries follow.
When 1: Indicates that the current operation is the last in
the chain.
Reset value: Undefined.
Registers
7-21