21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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Page 114/159:

Control Register Offset 90h/B0h

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Registers
7.3.5
DMA Channel
The DMA channel n control register (n = 1 or 2) contains values that control the DMA channels for
the duration of a chain operation.
Dword Bit
Name
0
Channel enable
1
2
Channel transfer done
3
Channel error
4
Channel initial
descriptor in register
6:5
Channel PCI read type
7-24
Control Register—Offset 90h/B0h
n
R/W
Description
R/W
When 0: Channel not active.
When written from 0 to 1: Channel fetches the first
descriptor block (unless channel initial descriptor in
register bit [4] of this register is a 1), and then performs
DMA operations until it does a transfer with the end-of-
chain bit equal to 1. This bit is cleared internally when
channel chain done is set.
Reset value: 0.
R
Read only as 0.
W1C
Indicates that a transfer has completed, that is, the
transfer count from one of the descriptors has reached 0.
Reset value: 0.
W1C
Indicates that the channel detected either a PCI master
abort, target abort, or parity error during a PCI transfer, or
bad SDRAM parity during a SDRAM read. When set, the
channel stops operation regardless of the byte count and/
or end-of-chain bits.
Reset value: 0.
R/W
When 0: Indicates that the channel must read the first
descriptor from SDRAM.
When 1: Indicates that the SA-110 has written the first
descriptor to the channel registers. Channel reads of
subsequent descriptors, if any, are not affected by this bit.
Note that if this bit is set, the DAC register must be loaded
along with the other transfer parameters if a nonzero
value is required.
Reset value: Undefined.
R/W
This field is only meaningful if the transfer direction is PCI
to SDRAM, that is, reads are from the PCI bus. It defines
the command type that should be used during the PCI
reads.
• 00=Memory read
• 01=Memory read line
• 10=Memory read multiple
• 11=Memory read multiple
Reset value: Undefined.
21285 Core Logic for SA-110 Datasheet
(Sheet 1 of 2)