21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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7.3.24
X-Bus Cycle/Arbiter Register—Offset 148h
This register is used either to control the parallel port (X-Bus) or the internal PCI Arbiter. The
choice is based on the value latched on ma[7] at reset.
When X-Bus is selected (ma[7]=1), the register contents are as follows.
Dword Bit
Name
2:0
Device 0 cycle length
5:3
Device 1 cycle length
8:6
Device 2 cycle length
11:9
Device n cycle length
13:12
Strobe shift divisor
22:14
23
PCI Arbiter
27:24
Interrupt input level
30:28
X-Bus chip select
31
PCI interrupt request
21285 Core Logic for SA-110 Datasheet
R/W
Description
R/W
Contains the number of X-Bus cycles for an access to the
X-Bus device in xcs_l[0] range.
Reset value: 0.
R/W
Contains the number of X-Bus cycles for an access to the
X-Bus device in xcs_l[1] range.
Reset value: 0.
R/W
Contains the number of X-Bus cycles for an access to the
X-Bus device in xcs_l[2] range.
Reset value: 0.
R/W
Contains the number of X-Bus cycles for an access to the
X-Bus device in no chip select range.
Reset value: 0.
R/W
fclk_in is divided by the value in this field to determine the
frequency of the clock that is used to time the cycle length
and shift the strobe mask.
• 00=1
• 01=2
• 10=3
• 11=4
Reset value: 0.
R
Read only as 0.
R
Read only as 0. Allows software to determine that the
X-Bus is selected.
R/W
These bits control the assertion level of irq_in_l[3:0]. The
values are 0 for low assertions and 1 for high assertions.
Reset value: 0.
R/W
These bits control the assertion level of xcs_l[2:0]. The
values are 0 for low assertions and 1 for high assertions.
Reset value: 0.
R/W
This bit controls the assertion level of pci_irq_l when used
as an input pin. The value is 0 for low assertion and 1 for
high assertion.
Reset value: 0.
Registers
7-41