21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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Page 19/159:

ROM Signals

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2.3

ROM Signals

Table 2-5
describes signal outputs that are used for accessing the ROM. Refer to
additional ROM address bit connections. While the ROM is being accessed, signal rom_ce_l is
asserted. Refer to
Section 4.2
Table 2-5. ROM Signals
Signal Name
Type
A[31]
ICOCZ
A[30]
ICOCZ
A[29:28]
ICOCZ
rom_ce_l
OCZ
2.4
SDRAM Signals
The timing of the SDRAM signals is referenced to the sdclk. The SDRAM data lines may be
directly connected to D[31:0], or through transceivers, depending on the number of SDRAM chips.
Table 2-6
describes the SDRAM signals.
Note: The term array is used to represent a group of SDRAM chips that share a common chip select.
Table 2-6. SDRAM Signals (Sheet 1 of 2)
Signal Name
Type
ma[12:0]
ICOCZ
ba[1:0]
OCZ
cmd[2:0]
OCZ
dqm[3:0]
OCZ
cs_l[3:0]
OCZ
21285 Core Logic for SA-110 Datasheet
for a description of the address and data bus signals.
Description
ROM write enable. This signal allows data to be stored in a flash ROM.
ROM output enable. This signal allows the ROM to output data.
Two low address bits of ROM.
Table 4-4
ROM chip enable. Chip enable is asserted by the 21285 during ROM
accesses.
Description
Memory addresses. ma[12:0] provides multiplexed row and column addresses
to the SDRAMs. Some of the ma pins are used at reset to latch configuration
information. Refer to
Table
2-7.
Bank addresses. Selects SDRAM bank.
Command lines. SDRAM row address strobe (RAS), column address strobe
(CAS), and write enable (WE).
Masks. Control write operations for each byte.
dqm[3] controls D[31:24]
dqm[2] controls D[23:16]
dqm[1] controls D[15:8]
dqm[0] controls D[7:0]
Chip selects. Selects the four arrays of SDRAM.
Signal Description
Section 4.2.1
for
describes the use of these bits.
2-5