21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
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Signal Description
Table 2-6. SDRAM Signals (Sheet 2 of 2)
Signal Name
Type
d_wren_l
OCZ
parity[3:0]
ICOCZ
sdclk[3:0]
OCZ
Table 2-7
describes the ma signals that are inputs when nRESET is asserted, and are latched at the
deassertion of nRESET. These signals are used to control the configuration of various chip
features. The pins have an internal pull-up resistor, therefore, any pins that are not terminated are
considered to be a logical 1. A pull-down resistor can be used to supply a logical 0.
Note: If external buffering is used on the ma pins, the internal pull-up resistor may be inadequate to force
a reliable logic level on ma[8:2]. This occurs because buffers such as 74LVT16244A contain
internal bus hold circuitry on their input pins that will force an input high or low if it attempts to
float. The pull-up resistor internal to the 21285 is unable to supply enough current to overcome the
hysterisis in the bus hold circuitry. In this case, a 4.7 K pull-up or pull-down resistor should be
fitted externally on each of the ma[8:2] pins.
Table 2-7. ma Signals (Sheet 1 of 2)
Signal Name
Type
ma[8]
ICOCZ
ma[7]
ICOCZ
ma[6]
ICOCZ
2-6
Description
SDRAM data bus buffer control. Used as the direction control for an optional
data bus buffer between the SDRAM and the 21285/SA-110. Asserted during
writes to the SDRAM.
Byte parity for D[31:0]. Used for SDRAMs if enabled in the SDRAM timing
register.
parity[3] for D[31:24]
parity[2] for D[23:16]
parity[1] for D[15:8]
parity[0] for D[7:0]
These signals should not be left floating. If SDRAM parity is not used; connect
them to V
or V
. If parity is used, then bus sustainers are required.
ss
dd
SDRAM clocks. These clocks are internally buffered versions of osc. There is
one clock for each array of SDRAM chips.
Description
Intel reserved test mode.
When 1: Normal operation.
When 0: Enable Intel reserved test mode.
X-Bus/Arbiter mode.
When 0: X-Bus/Arbiter pins are used for the internal PCI arbiter.
When 1: X-Bus/Arbiter pins are used for the X-Bus.
Blank ROM program mode.
When 1: Normal mode. The 21285 does not allow access from the
PCI until after the 21285 CSRs have been initialized from the SA-110.
When 0: Blank ROM mode. The 21285 allows access from the PCI
prior to the normal initialization from the SA-110. See
for a description of all the specific differences.
21285 Core Logic for SA-110 Datasheet
Section 4.2.5