21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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3.2.3
Memory Read, Memory Read Line, Memory Read Multiple to
SDRAM
PCI memory read from SDRAM occurs if the PCI address matches the SDRAM base address
register (at offset 18h) or the CSR base address register (at offset 10h with an offset greater than
FFFh), and the command is either a memory read, memory read line, or memory read multiple.
The read is completed as a PCI delayed read. On the first occurrence of the read, the 21285 signals
a retry to the PCI master. If the delayed read latch is not full, the 21285 latches the address and
command, and places it into the Inbound FIFO.
When the address reaches the head of the FIFO, the 21285 reads the SDRAM.
Table 3-1
describes how the SDRAM address is derived from the PCI address.
The amount of data that is read is a function of the following PCI commands:
Memory read—One to four Dwords depending on the PCI address.
PCI Address Bits [3:2]
00
01
10
11
Memory read line—Up to one cache line. The amount of data read is from the PCI address up
to the top Dword of the cache line. If the cache line size is not 4 or 16, then the value of 8 is
used for the cache line.
Memory read multiple—Up to 32 Dwords. The amount of data read is from the PCI address
up to the top Dword of the 32 Dword aligned block.
Exceptions to the above rules for the memory read line and memory read multiple commands are:
If the PCI address bits [1:0] are not 00 (that is, not linear increment mode), read only one
Dword.
Reads do not cross a SDRAM page boundary.
When the read data is read from SDRAM into the PCI read FIFO, the 21285 begins decrementing
its discard timer. If the PCI bus master has not repeated the read by the time the discard timer
reaches zero, the 21285 discards the read data, invalidates the delayed read address, and sets a bit
in the SA-110 control register (which interrupts the SA-110 if enabled). The discard timer counts
15
2
(32768) PCI clocks.
When the master repeats the read command, the 21285 compares the address and checks that the
command is a memory read, a memory read line, or a memory read multiple (that is, all memory
read command types are aliased for a match). If there is a match, the response is as follows:
If the read data has not yet been read from SDRAM, the response is retry.
If the read data has been read from SDRAM, assert trdy_l and deliver the data. If the master
attempts to continue the burst past the amount of data read from SDRAM, the 21285 target
disconnects.
21285 Core Logic for SA-110 Datasheet
Number of Dwords Read
4
3
2
1
Transactions
3-9