21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 

Specifications of 21285-AB

CaseBGADc99+/00+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
Page 46/159:

Memory Write to ROM

Download datasheet (780Kb)Embed
PrevNext
Transactions
This read is completed as a delayed read. On the first occurrence of the read, the 21285 signals a
retry to the PCI master. If the delayed read latch is not full, the 21285 latches the address and
command, and places it into the Inbound FIFO.
When the read address reaches the head of the FIFO, the 21285 reads the SDRAM at the address in
the inbound free list head pointer register (for offset 40h), or the outbound post list head pointer
register (for offset 44h). If the list being read is empty, the value FFFFFFFFh is substituted for the
data read from the SDRAM.
When the master repeats the read command, the 21285 compares the address and checks that the
command is a memory read, a memory read line, or a memory read multiple (that is, all memory
read command types are aliased for a match). If there is a match, the response is as follows:
If the read data has not yet been read from SDRAM, the response is retry.
If the read data has been read from SDRAM, assert trdy_l and deliver the data. If the PCI
master attempts to do a burst longer than one data phase, the 21285 target disconnects.
If the delayed read latch is full and a new read from a different address is attempted, that read gets
a retry and no change is made in the delayed read latch. In other words, the new read does not
displace the in-progress read.
If the PCI address matches the CSR I/O base address register (see
command is an I/O read, and the register offset is either 40h or 44h. The 21285 returns 0 for read
data.
For more information about CSR and I
3.2.10

Memory Write to ROM

PCI memory write to ROM occurs when the PCI address matches the expansion ROM base
address register, bit [0] of the expansion ROM base address register is a 1, and the PCI command is
either memory write or memory write and invalidate. The PCI memory write address and data is
collected in the Inbound FIFO to be written to ROM at a later time. The 21285 target disconnects
after one data phase.
Only a single ROM write cycle is done regardless of the PCI byte enable and the ROM width field
settings in the SA-110 control register. In addition, the data to be written must be put into the
proper byte lanes by software. See
way in which the ROM write address is derived from the PCI address.
3.2.11
Memory Read to ROM
PCI memory read to ROM occurs when the PCI address matches the expansion ROM base address
register, bit [0] of the expansion ROM base address register is a 1, and the PCI command is either a
memory read, memory read line, or memory read multiple.
The read is completed as a PCI delayed read. On the first occurrence of the read, the 21285 signals
a retry to the PCI master. If the delayed read latch is not full, the 21285 latches the address and
command, and places it into the Inbound FIFO.
3-12
Section
O registers, see
Chapter
7.
2
Section 4.2
for a description of the ROM write cycle and the
21285 Core Logic for SA-110 Datasheet
7.1.12), the PCI