21285-AB Rom Addressing - Intel Corporation
Manufacturer Part Number
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Specifications of 21285-AB
SDRAM and ROM Operation
Table 4-4. ROM Addressing
Word (2 bytes)
Dword (4 bytes)
During ROM accesses from the SA-110, the 21285 latches the address and drives it back onto A.
shows how the ROM address is derived from the SA-110 address.
Table 4-5. ROM Address Generation for SA-110 Accesses
During a ROM access from the PCI, A is driven by the 21285.
address is derived from the PCI address.
Table 4-6. ROM Address Generation for PCI Accesses
Controlled by the 21285 depending upon the ROM width (refer to Sections 4.2.2 and 4.2.3).
If the corresponding bit of the expansion ROM base address mask register is a 0, the address bit
is 0. If the corresponding bit of the expansion ROM base address mask register is a 1, use the
PCI address bits [19:6].
If the PCI accesses the lower 32 bytes of ROM, this address is the inverse of PCI address bit
. Otherwise, it is equal to PCI address bit .
PCI address bits [4:2]
The reason for the conditional inversion of bit 5 is that the SA-110 needs to read a vector from
ROM address 0h, and the PCI requires the expansion ROM header to be at ROM address 0h. To
accommodate both needs, ROM addresses 20h through 3Fh are swapped with 0h through 1Fh
when addressed from the PCI. The SA-110 vector should be placed in ROM address 0h, and the
PCI expansion ROM header should be placed in ROM address 20h through 3Fh, as seen from the
ROM Address [23:2]
ROM Address 
Controlled by the 21285 depending upon the ROM width (refer to Sections 4.2.2
Same value that was driven by the SA-110.
Initial value as driven by the SA-110. For cache line fills, subsequent values are
generated by the 21285.
Driven, but not defined.
ROM Address 
shows how the ROM
21285 Core Logic for SA-110 Datasheet