21285-AB Blank Rom Programming - Intel Corporation
Manufacturer Part Number
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Specifications of 21285-AB
SDRAM and ROM Operation
All ROM address, data, and control signals are controlled synchronously to fclk_in.
The ROM read timing is as follows:
At the start of the cycle, the address is driven and rom_ce_l is asserted.
After one fclk_in cycle, rom_oe_l is asserted (this signal is driven on A).
After a further ROM access time fclk_in cycle, the ROM data is latched, rom_oe_l negates,
and the address changes.
If another read is required (either to pack a Dword or to fulfill an SA-110 cache line fill), then
the new address remains valid for ROM burst time fclk_in cycles and rom_oe_l is reasserted
after one fclk_in cycle. This means that rom_oe_l is negated for the first fclk_in cycle of the
access. This is a deliberate policy to provide compatibility with some designs of the ROM
When the final read has been completed, there is a delay of ROM tristate time fclk_in cycles
before another device is enabled onto the D bus. This feature allows ROMs with slow data
turn-off times to be accommodated.
The ROM write timing is as follows:
At the start of the cycle, the address and data are driven and rom_ce_l is asserted.
After two fclk_in cycles, rom_we_l is asserted (this signal is driven on A).
After the address has been valid for a total of 1 + ROM access time fclk_in cycles, rom_we_l
After a further fclk_in cycle, rom_ce_l negates and the address and data go invalid.
The ROM tristate time delay is imposed after ROM writes, but serves no useful purpose.
Blank ROM Programming
The 21285 has a mode that allows programming of blank Flash ROMs in place on a circuit board.
This mode is enabled if both ma and pci_cfn are 0 when the 21285 is reset. When this mode is
nRESET is asserted by the 21285 to keep the SA-110 in reset state. (This is necessary since
there may be no code in the ROM yet.)
The initialize complete bit  in the SA-110 control register is set internally by the 21285.
This allows the 21285 to complete type 0 configuration accesses.
The expansion ROM base address mask is reset to 00F00000h (this is the normal default)
causing the expansion ROM base address to request 16MB. This is the largest size ROM
The SDRAM base address mask is reset to 00FC0000h causing the SDRAM base address to
request 16MB. This guarantees that there will be a 16MB address region allocated in PCI
address space, but not used by the device. Flash programming software can reallocate that
space to the ROM when the BIOS has not allocated any address space to the ROM.
The normal PCI configuration software running on the host processor can load both the
expansion ROM base address register and the command register, allowing the 21285 to
respond to PCI memory cycles. The host processor can then perform normal ROM writes.
21285 Core Logic for SA-110 Datasheet