21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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Byte Enables

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SA-110 Operation
Table 5-1. SA-110 4GB Address Mapping
Function
X-Bus XCS1
X-Bus XCS2
X-Bus no CS
Reserved
ROM
CSR space
Reserved
SA-110 cache flush
Reserved
Outbound write flush
PCI IACK/special space
PCI type 1 configuration
PCI type 0 configuration
PCI I/O space
Reserved
PCI memory space
5.1.2

Byte Enables

During SA-110 bus cycles, the byte enables are driven on A[1:0] concatenated with MAS[1:0]
(SA-110 must be in enhanced mode). The byte enables are used during SDRAM writes and PCI
writes and reads, with the exception of memory read line and memory read multiple, which assert
all PCI byte enables despite the state of the SA-110 byte enables.
5.1.3
SA-110 Bus Arbiter
The purpose of the SA-110 bus arbiter is to choose which of several operations to perform when
more than one is possible at a given time.
The operations that use the SA-110 bus are as follows:
Refresh SDRAM
SA-110 originated operations
— Read SDRAM
— Write SDRAM
— Read ROM
— Write ROM
— Read CSR
— Write CSR
— Read PCI
5-2
(Sheet 2 of 2)
Start Address
End Address
Size
4001 1000h
4001 1FFFh
4KB
4001 2000h
4001 2FFFh
4KB
4001 3000h
4001 3FFFh
4KB
4001 4000h
40FF FFFFh
4100 0000h
41FF FFFFh
16MB
4200 0000h
420F FFFFh
1MB
4210 0000h
4FFF FFFFh
5000 0000h
50FF FFFFh
16MB
5100 0000h
77FF FFFFh
7800 0000h
78FF FFFFh
16MB
7900 0000h
79FF FFFFh
16MB
7A00 0000h
7AFF FFFFh
16MB
7B00 0000h
7BFF FFFFh
16MB
7C00 0000h
7C00 FFFFh
64KB
7C01 0000h
7FFF FFFFh
8000 0000h
FFFF FFFFh
2GB
21285 Core Logic for SA-110 Datasheet