21285-AB Determining Priority - Intel Corporation

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21285-AB

Manufacturer Part Number
21285-AB
Description
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Manufacturer
Intel Corporation
Datasheet

Specifications of 21285-AB

Case
BGA
Dc
99+/00+
Functional Units
Figure 6-1. Secondary Arbiter Example
m0
Note:
B – 21285
m x – Bus Master Number
lpg – Low-Priority Group
Arbiter Control Register = 0011b
Each bus master, including the 21285, can be configured to be in either the low-priority group or
the high-priority group as determined by the value of the corresponding priority bit in the arbiter
control register. Each master has a corresponding bit. If the bit is a 1, the master is assigned to the
high-priority group; if the bit is a 0, the master is assigned to the low-priority group. If all the
masters are assigned to one group, the algorithm defaults to a straight rotating priority among all
the masters.
6.1.2

Determining Priority

Priorities are reevaluated every time frame_l is asserted, that is, at the start of each new transaction
on the PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the
grant signal corresponding to the highest priority request that is asserted. If a grant for a particular
request is asserted, and a higher priority request subsequently asserts, the arbiter deasserts the
asserted grant signal and asserts the grant corresponding to the new higher priority request on the
next PCI clock cycle. When priorities are reevaluated, the highest priority is assigned to the next
highest priority master relative to the master that initiated the previous transaction. The master that
initiated the last transaction now has the lowest priority in the group.
If the arbiter detects that an initiator has failed to assert frame_l after 16 cycles of both grant
assertion and PCI bus idle condition, the arbiter deasserts the grant. That master does not receive
any more grants until it deasserts its request for at least one PCI clock cycle.
To prevent bus contention, if the PCI bus is idle, the arbiter never asserts one grant signal in the
same PCI cycle in which it deasserts another. It deasserts one grant, and then asserts the next grant
no earlier than one PCI clock cycle later. If the PCI bus is busy, that is, either frame_l or irdy_l is
asserted, the arbiter can deassert one grant and assert another during the same PCI clock cycle.
6.2
DMA Channels
There are two DMA channels; each of which can move blocks of data from SDRAM to PCI or PCI
to SDRAM. The DMA channels read parameters from a list of descriptors in memory, perform the
data movement, and stop when the list is exhausted.
6-2
m1
lpg
B
m2
m3
FM-05867.AI4
21285 Core Logic for SA-110 Datasheet

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