21285-AB Serial Port - Intel Corporation
Manufacturer Part Number
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Specifications of 21285-AB
System software can use the watchdog as follows. Set timer 4 for periodic interrupts and disable
the interrupt on nIRQ/nFIQ. A periodic process (based on one of the other timers) would write to
Timer4Load. If that process ever fails to write to Timer4Load within the countdown time, then
both the SA-110 and the 21285 reset.
Once the watchdog enable bit is set, it can only be cleared by a chip reset.
The serial port is a general-purpose, full-duplex, universal asynchronous receivertransmitter
(UART), which supports similar functionality to the 16C550 UART. It can operate at baud rates
from approximately 225 bps to approximately 200 Kbps; the exact range is dependent upon the
fclk_in frequency. It supports five to eight bits of data; odd, even, or no parity; one start bit; either
one or two stop bits; and can transmit a continuous break signal.
The external pins dedicated to this interface are tx and rx. Modem control signals (RTS, CTS,
DTR, and DSR) are not implemented.
The UART registers are only accessible to the SA-110; these registers cannot be accessed via the
A 16-entry, 8-bit FIFO is used to buffer outgoing data, and a 16-entry, 10-bit FIFO is used to buffer
incoming data (two bits per entry are used to store framing and parity error flags for each character
received). It is possible to provide single data buffering by disabling all FIFO entries but one.
Following reset, the UART is disabled. Operation is initialized by the following:
1. Program the UART control register with the desired mode of operation.
2. Write the H_UBRLCR, L_UBRLCR, and M_UBRLCR registers setting up baud rate, parity,
stop bits, word length, and enable FIFO.
3. Set the enable bit in the UARTCON register.
Once programmed, transmission and reception of data begins on the transmit (tx) and receive (rx)
Nonreturn to zero (NRZ) encoding is used by the UART. Each data frame is between 7 and 12 bits
long depending on the size of the data programmed, if parity is enabled, and if a second stop bit is
enabled. The frame begins with a start bit that is represented by a high-to-low transition. Next,
either 5, 6, 7, or 8 bits of data are transmitted beginning with the least significant bit. An optional
parity bit follows, which is set if even parity is enabled and an even number of ones exist within the
data byte, or if odd parity is enabled and the data byte contains an odd number of ones. The data
frame ends with either one or two stop bits (selected within the control register) that is represented
by one or two successive bit periods of a logic one.
21285 Core Logic for SA-110 Datasheet