21285 Core Logic for SA-110 Datasheet
Note: The received data must be read first (UARTDR) followed by the status error associated with the
Reading from the RXSTAT provides the error status associated with the data received on
UARTDR. Flags in this register indicate error conditions, such as overrun, framing, and parity
errors, which occurred during the unpacking of a received frame. Each entry in the receive FIFO
contains two error bits that correspond to the data stored within the same FIFO entry. The parity
error bit is set when parity is enabled (PE = 1) and the parity type programmed using OES does not
correspond to the parity check of the incoming serial data stream that is calculated by the receive
logic. The parity error bit is set when the expected parity does not match the received parity. The
framing error bit is set when the stop bit, within a frame of incoming serial data, is a zero instead of
data (RXSTAT). This read sequence cannot be reversed.
This bit is set if a framing error (FE) occurred.
This bit is set if a parity error (PER) occurred.
The overrun error (ORE) bit is set if more data is received by the UART
when the FIFO is full. (It is cleared by reading the UARTDR register.)
Read only as 0.