PEB2054NV1.0 Infineon Technologies AG, PEB2054NV1.0 Datasheet

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PEB2054NV1.0

Manufacturer Part Number
PEB2054NV1.0
Description
ISDN Controller, S/T, Commercial, 44-LDCC
Manufacturer
Infineon Technologies AG
Datasheet
ICs for Communications
Extended PCM Interface Controller
EPIC
PEB 2055 / PEF 2055
EPIC
PEB 2054 / PEF 2054
User’s Manual 02.97
®
®
-1
-S
Versions A3
Versions 1.0

Related parts for PEB2054NV1.0

PEB2054NV1.0 Summary of contents

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ICs for Communications Extended PCM Interface Controller ® EPIC -1 PEB 2055 / PEF 2055 ® EPIC -S PEB 2054 / PEF 2054 User’s Manual 02.97 Versions A3 Versions 1.0 ...

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PEB 2055 PEF 2055 Revision History: Previous Release: Page (in Page Subjects (major changes since last revision) Previous (in User’s Release) Manual) Edition 02.97 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, ...

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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.2.6.8 Version Number Status Register (VNSR .82 5 Application Hints . ...

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Table of Contents 5.7 Synchronous Transfer Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Overview The PEB 2055 (Extended PCM Interface Controller highly integrated controller circuit optimized for analog and ISDN line card and central switches applications. The EPIC-1 provides the circuitry necessary to manage digital (ISDN or ...

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Extended PCM Interface Controller ® ® EPIC -1, EPIC -S Versions A3 (PEB 2055), V1.0 (PEB 2054) 1.1 Features Switching • Board Controller for up to – 32 ISDN or 64 analog subscribers (PEB 2055) – 16 ISDN or 32 ...

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Handling of Layer-1 Functions • Change detection for C/I-channel (IOM-configuration) or feature control (SLD-configuration) • Double last-look logic for C/I-channel (IOM-2 analog configuration) • Additional last-look logic for feature control (SLD-configuration) • Buffered monitor (IOM-configuration) or signaling channel (SLD-configuration) Bus ...

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R/ ALE INT DCL FSC N.C. N.C. DU1 DU0 A3 Figure 2 Pin Configuration EPIC Semiconductor Group PEB 2054 34 R EPIC ...

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Pin Definitions and Functions Pin No. Symbol Input (I) EPIC-S EPIC WR AD0 AD1 AD2 AD3, D3 ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) EPIC-S EPIC 17 17 PDC 6 6 RxD0 5 5 RxD1 4 4 RxD2 3 3 RxD3 9 9 TxD0 11 11 TxD1 13 13 TxD2 15 15 TxD3 ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) EPIC-S EPIC 40 40 DD0/SIP0 41 41 DD1/SIP1 - 42 * DD2/SIP2 - 43 * DD3/SIP3 ...

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Logic Symbols DCL FSC DU CFI Port CFI Port CFI Port CFI Port 3 DD Figure 3 Logic Symbol of the EPIC Semiconductor Group EPIC -1 ...

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DCL FSC DU CFI Port CFI Port 1 DD Figure 4 Logic Symbol of the EPIC Semiconductor Group EPIC -S 1 AD7...0 A3... ALE ® PEB 2055 PEF 2055 ...

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Functional Block Diagram DCL / SCL FSC / DIR SIP0 SIP SIP SIP SIP SIP 6 DD ...

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Using the EPIC-S The EPIC-S is based on the same technology as the EPIC-1 aside from only providing CFI port 0 and CFI port 1. Therefore this User’s Manual applies to both, the EPIC-S and the EPIC-1. When using ...

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System Integration and Application The main application fields of the EPIC are: – Digital line cards with different architectures, – Central control units of key systems, – Analog line cards, – Concentrators. 1.7.1 Digital Line Card 1.7.1.1 Switching, Layer-1 ...

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R IOM -2 Interface IDEC IDEC Data s-Data P p-Data Figure 6 Line Card Architecture for Completely Decentral D-Channel Processing Semiconductor Group Example Frame Structure EPIC s-Data HSCX 19 PEB 2055 PEF ...

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Central D-Channel Processing In this application the EPIC not only switches the B-channels and performs the C/I- and monitor channel control function, but switches also the D-channel data onto the system highway. In upstream direction the EPIC can combine ...

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Mixed D-Channel Processing, Signaling Decentralized, Packet Data Centralized Another possibility is a mixed architecture with centralized packet data and decentralized signaling handling. This is a very flexible architecture which reduces the dynamic load of central processing units by evaluating ...

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Alternatively, the packet and collision data can be directly exchanged between the IDECs and the PCM-highway. Thus, the full 32 subscriber switching capability of the EPIC is retained. R IOM -2 Interface Figure 9 Line Card Architecture for Mixed D-Channel ...

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Analog Line Card Together with the highly flexible Siemens codec filter circuits SLICOFI, SICOFI, SICOFI-2 or SICOFI-4 the EPIC constitutes an optimized analog subscriber board architecture. The EPIC-1 handles the signalling and voice data for subscriber ...

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Packet Handlers The EPIC is an important building block for networks based on either central, decentral or mixed signaling and packet data handling architectures. Its flexibility allows for the modification of the packet handling architecture according to the changing ...

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This figure shows one EPIC connecting four PCM highways to one packet handler internal highway. These highways are accessed by the IDECs, which are 4 channel HDLC controller and handle the packets. If more than four PCM highways shall be ...

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PCM Highways Figure 13 Centralized Packet Handler with 3 Internal Highways In some applications an additional collision resolution signal is required for the HDLC controllers. This information can be demultiplexed from the ...

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Functional Description In the following chapters the functions of the PEB 2055 will be covered in more detail. 2.1 Bus Interface All registers and the FIFOs of the EPIC are accessible via the flexible bus interface supporting Siemens / ...

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In order to simplify the use of 8- and 16-bit Siemens / Intel type CPUs, different register addresses are defined in multiplexed and demultiplexed bus mode (see chapter 4.1). In the multiplexed mode even addresses are used (AD0 always 0). ...

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Configurable Interface In order to optimize the on-board interchip communication, a very flexible serial interface is available. It formats the data transmitted or received at the DDn-, DUn- or SIPn-lines. Although it is typically used in IOM-2 or SLD-configuration ...

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The CFI reads periodically the control memory and uses the extracted values as pointers to write to the upstream (read from the downstream) data memory (random access). In the case of C/I- or signaling channel applications the corresponding data is ...

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Pre-processed Channels, Layer-1 Support The EPIC supports the monitor/feature control and control/signalling channels according to SLD or IOM-2 interface protocol. The monitor handler controls the data flow on the monitor/feature control channel either with or without an active handshake ...

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Operational Description The EPIC, designed as a flexible line-card controller, has the following main applications: – Digital line cards, with the CFI typically configured as IOM-2, IOM-1 (MUX) or SLD. – Analog line cards, with the CFI typically configured ...

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Interrupts An interrupt of the EPIC is indicated by activating the INT line. The detailed cause of the request can be determined by reading the ISTA register. The INT-output is level active. It remains active until all interrupt sources have ...

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EPIC ® Operation The EPIC is principally an intelligent switch of PCM data between two serial interfaces, the system interface (PCM interface) and the configurable interface (CFI 128 channels per direction can be switched dynamically between the ...

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PCM-Interface The serial PCM interface provides up to four duplex ports consisting each of a data transmit (TxD), a data receive (RxD) and a tristate control (TSC) line. The transmit direction is also referred to as the upstream direction, ...

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The offset can then be programmed such that PFS marks any bit number of the external frame. Furthermore it is possible to select either the rising or falling PDC-clock edge for transmitting and sampling the PCM-data. Usually, the repetition rate ...

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The number of time slots per 8-kHz frame is programmable from 2 to 128. In other words, the CFI-data rate can range between 128 kbit 8.192 Mbit/s. Since the overall switching capacity is limited to 128 time slots ...

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Switching Functions The major tasks of the EPIC part is to dynamically switch PCM data between the serial PCM interface, the serial configurable interface (CFI) and the parallel P interface. All possible switching paths are shown in figure 18. ...

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Time slot switching is always carried out on 8-bit time slots, the actual position and number of transferred bits can however be limited to 4-bit or 2-bit sub time slots within these 8-bit time slots. On the CFI side, only ...

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To program a pair of pre-processed channels the correct code for the selected handling scheme must be written to the CM. Figure 19 gives an overview of the available pre- processing codes and their application. For further detail, please refer ...

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Synchronous Transfer For two channels, all switching paths of figure 18 can also be realized using Synchronous Transfer. The working principle is that the P specifies an input time slot (source) and an output time slot (destination). Both source and ...

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Initialization Procedure For proper initialization of the EPIC the following procedure is recommended: 3.5.1 Hardware Reset A reset pulse can be applied at the RES pin for at least 4 PDC clock cycles. The reset pulse sets all registers ...

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Initialization of Pre-processed Channels After the CM reset, all CFI time slots are unassigned. If the CFI is used as a plain PCM interface, i.e. containing only switched channels (B channels), the initialization steps below are not required. The ...

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CFI-port 0, time slot 2 (even), downstream MADR = FF H MAAR = 08 H MACR = 78 H Wait for STAR:MAC = 0 CFI-port 0, time slot 3 (odd), downstream MADR = FF H MAAR = 09 H MACR ...

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Initialization of the Upstream Data Memory (DM) Tristate Field For each PCM time slot the tristate field defines whether the contents of the DM data field are to be transmitted (low impedance), or whether the PCM time slot shall ...

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Detailed Register Description 4.1 Register Address Arrangement Group Reg. Access Name PMOD RD/WR PBNR RD/WR POFD RD/WR PCM interface POFU RD/WR PCSR RD/WR PICM RD CMD1 RD/WR CMD2 RD/WR CBNR RD/WR CFI CTAR RD/WR interface CBSR RD/WR CSCR RD/WR ...

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Register Address Arrangement (cont’d) Group Reg. Access Name MFAIR RD Monitor/ feature MFSAR WR control MFFIFO RD/WR CIFIFO RD TIMR WR STAR RD CMDR WR Status/ ISTA RD control MASK WR OMDR RD/WR VNSR RD/WR Semiconductor Group Address Address ...

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Detailed Register Description 4.2.1 PCM Interface Registers 4.2.1.1 PCM-Mode Register (PMOD) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 PMD1 PMD0 PMD1..0 PCM Mode. Defines the actual number of PCM ports, ...

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AIS1..0 Alternative Input Selection. These bits determine the relationship between the physical pins and the logical port numbers. The logical port numbers are used when programming the switching functions. Note: In PCM-mode 0 these bits may not be set! PCM ...

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Bit Number per PCM-Frame (PBNR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 BNF7 BNF6 BNF5 BNF7..0 Bit Number per PCM Frame. PCM-mode 0: BNF7..0 = number of bits – 1 ...

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PCM-Offset Upstream Register (POFU) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 OFU9 OFU8 OFU7 OFU9..2 Offset Upstream bit 9…2. These bits together with PCSR:OFU1..0 determine the offset of the PCM ...

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PCM-Input Comparison Mismatch (PICM) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 IPN TSN6 TSN5 IPN Input Pair Number. This bit denotes the pair of ports, where a bit mismatch occurred. ...

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Configurable Interface Registers 4.2.2.1 Configurable Interface Mode Register 1 (CMD1) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 CSS CSM CSP1 CSS Clock Source Selection. 0…PDC and PFS are used as ...

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CMD1..0 CFI Mode1,0. Defines the actual number and configuration of the CFI ports. CMD1..0 CFI Mode where N = number of time slots in a PCM frame CIS1..0 CFI Alternative Input Selection. ...

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Configurable Interface Mode Register 2 (CMD2) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 FC2 FC1 FC2..0 Framing output Control. Given that CMD1:CSS = 0, these bits determine the position of ...

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CFI Last Time-Slot of a Frame Frame RCL DCL DCL DCL FSC FSC FSC FSC FSC Figure 20 Position of the FSC Signal for FC Modes and 6 Time-Slot CFI 0 1 Frame FSC FSC RCL ...

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Application examples: FC2 FC1 FC0 For further details on the framing output control please refer to ...

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Configurable Interface Bit Number Register (CBNR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 CBN7 CBN6 CBN5 CBN7..0 CFI Bit Number 7..0. The number of bits that constitute a CFI frame ...

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Configurable Interface Bit Shift Register (CBSR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 0 CDS2 CDS1 CDS2..0 CFI Downstream bit Shift 2..0. From the zero offset bit position (CBSR = ...

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Configurable Interface Subchannel Register (CSCR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 SC31 SC30 SC#1..#0 CFI Subchannel Control for logical port #. The subchannel control bits SC#1..SC#0 specify separately for ...

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Memory Access Registers 4.2.3.1 Memory Access Control Register (MACR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RWS MOC3 MOC2 With the MACR the P selects the type of memory (CM ...

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Writing data to the upstream DM data field (e.g. PCM idle code). Reading data from the upstream or downstream DM data field. MACR: RWS MOC3 MOC2 MOC3..0 defines the bandwidth and the position of the subchannel as shown below: ...

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Writing data to the upstream or downstream CM data and code field (e.g. switching a CFI to/from PCM connection). MACR The 4-bit code field of the control memory (CM) defines the functionality of a CFI time slot ...

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Pre-processed Applications Downstream: Application Decentral D channel handling Central D channel handling 6-bit Signaling (e.g. analog IOM) 8-bit Signaling (e.g. SLD) Upstream: Application Decentral D channel handling Central D channel handling 6-bit Signaling (e.g. analog IOM) 8-bit Signaling (e.g. ...

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Memory Access Address Register (MAAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 U/D MA6 The Memory Access Address Register MAAR specifies the address of the memory access. This address encodes ...

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Table 4 Time Slot Encoding for Control Memory Accesses CFI-mode 0 CFI-mode 1 CFI-mode 2 CFI-mode 3 4.2.3.3 Memory Access Data Register (MADR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MD7 ...

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Synchronous Transfer Registers 4.2.4.1 Synchronous Transfer Data Register (STDA) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MTDA7 MTDA6 MTDA5 The STDA register buffers the data transferred over the synchronous transfer ...

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Synchronous Transfer Receive Address Register A (SARA) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 ISRA MTRA6 MTRA5 The SARA register specifies for synchronous transfer channel A from which input interface, ...

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Synchronous Transfer Receive Address Register B (SARB) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 ISRB MTRB6 MTRB5 The SARB register specifies for synchronous transfer channel B from which input interface, ...

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Synchronous Transfer Transmit Address Register B (SAXB) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 ISXB MTXB6 MTXB5 The SAXB register specifies for synchronous transfer channel B to which output interface, ...

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CTA2..0 Channel Type A (B); these bits determine the bandwidth of the channel and CTB2..0 the position of the relevant bits in the time slot according to the table below. Note:Note that if a CFI time slot is selected as ...

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MF-Channel Subscriber Address Register (MFSAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MFTC1 MFTC0 SAD5 The exchange of monitor data normally takes place with only one subscriber circuit at a ...

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Monitor/Feature Control Channel FIFO (MFFIFO) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: empty bit 7 MFD7 MFD6 MFD5 The 16-byte bi-directional MFFIFO provides intermediate storage for data bytes to be transmitted or received over ...

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Timer Register (TIMR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 SSR TVAL6 TVAL5 The EPIC timer can be used for 3 different purposes: timer interrupt generation (ISTA:TIG), FSC multiframe generation ...

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Status Register (STAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MAC TAC The status register STAR displays the current state of certain events within the EPIC. The STAR register bits ...

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Command Register (CMDR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit Writing a logical CMDR register bit starts the respective operation. ST Start Timer. 0… no ...

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MFFR MFFIFO Reset. 0… no action 1… resets the MFFIFO and all operations associated with the MF handler (except for the search function) within 2 RCL periods. The MFFIFO is set into the state “MFFIFO empty”, write access enabled and ...

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Interrupt Status Register (ISTA) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 TIN SFI The ISTA register should be read after an interrupt in order to determine the interrupt source. TIN ...

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SIN Synchronous transfer Interrupt; The SIN interrupt is enabled if at least one synchronous transfer channel (A and/ enabled via the STCR:TAE, TBE bits. The SIN interrupt is generated when the access window for the P opens. After ...

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Operation Mode Register (OMDR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 OMS1 OMS0 OMS1..01 Operational Mode Selection; these bits determine the operation mode of the EPIC according to the following ...

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PSB PCM Standby. 0…the PCM interface output pins TxD0..3 are set to high impedance and those TSC pins that are actually used as tristate control signals are set to logical 1 (inactive). 1…the PCM output pins transmit the contents of ...

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Version Number Status Register (VNSR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit The VNSR register bits do not generate interrupts and are not modified by reading VNSR. The ...

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Application Hints 5.1 Introduction 5.1.1 IOM ® and SLD Functions IOM ® (ISDN Oriented Modular) Interface The IOM-2 standard defines an industry standard serial bus for interconnecting telecommunications ICs. The standard covers line card, NT1, and terminal architectures for ...

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Frames are delimited kHz frame synchronization signal (FSC). The bit timing and FSC position is identical to the non-multiplexed IOM-1 case. The line card version of the IOM transceivers (ISDN) or codecs (analog), and the line ...

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The terminal version of the IOM ISDN terminal and NT1 applications. It consists of three IOM channels, each containing four 8 bit time slots. The resultant data transfer rate is therefore 768 kbit/s and the data is clocked with a ...

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SLD (Subscriber Line Data) Interface The SLD bus is used by the EPIC to interface with the subscriber line devices. A Serial Interface Port (SIP) is used for the transfer of all digital voice and data, feature control and signaling ...

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The Characteristics of the Different IOM Two Groups • Timing characteristics and • Handling of special channels (C/I or signaling channel, monitor or feature control channel) The timing characteristics (data rate, clock rate, bit timing, etc. … ) are programmed ...

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Example: the EPIC reads an EOC message out of an IEC-Q (PEB 2091) device. The Control/Signaling handler can be adjusted to handle the following types of channels: • 4 bit ...

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Configuration of Interfaces 5.2.1 PCM Interface Configuration 5.2.1.1 PCM Interface Signals The PCM interface signals are summarized in table 7. Table 7 Pin No. Symbol 9 TxD0 11 TxD1 13 TxD2 15 TxD3 8 TSC0 10 TSC1 12 TSC2 ...

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PCM Bit Number Register bit 7 PBNR BNF7 BNF6 PCM Offset Downstream Register bit 7 POFD OFD9 OFD8 PCM Offset Upstream Register bit 7 POFU OFU9 OFU8 PCM Clock Shift Register bit 7 PCSR 0 OFD1 Operation Mode Register bit ...

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PCM Interface Characteristics In the following the PCM interface characteristics that can be programmed in the PCM interface registers are explained in more detail. PCM Mode PMOD: PMD1, PMD0 The PCM mode primarily defines the actual number of PCM ...

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PCM Bit Number PBNR:BNF7 … BNF0 The PCM data rate is determined by the clock frequency applied to the PDC pin and the clock rate selected by PMOD:PCR. The number of bits which constitute a PCM frame can be derived ...

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PCM Synchronization Mode PMOD:PSM The PCM interface is synchronized via the PFS signal. A transition from low to high of PFS synchronizes the PCM frame. It should be noted that the rising PFS edge does not directly synchronize the frame, ...

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PFS PDC TxD# 1st Bit 2nd Bit 3rd Bit TxD# 1st Bit 2nd Bit 3rd Bit RxD# 1st Bit 2nd Bit RxD# 1st Bit TxD# 1st Bit TxD# 1st Bit RxD# 1st Bit RxD# Figure 24 PCM Interface Framing Offset ...

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PFS PDC TxD# 1st Bit 2nd Bit TxD# 1st Bit 2nd Bit 3rd Bit RxD# 1st Bit 2nd Bit RxD# 1st Bit 2nd Bit TxD# 1st Bit TxD# 1st Bit RxD# 1st Bit RxD# 1st Bit Figure 25 PCM Interface ...

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Table 12 PCM Mode Offset Upstream, POFU, PCSR 0 OFU9 … (BNU + 23) 1 OFU9 … (BNU + 47) 2 OFU9 … (BNU + 95) Examples 1) In PCM mode 0, with a ...

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The PCM interface shall be clocked with a PDC having the same frequency as the data rate i.e. 2.048 MHz. Since the rising edge of PFS occurs at the same time as the rising edge of PDC recommended ...

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The PCM interface shall be clocked with a PDC having twice the frequency of the data rate i.e. 6144 kHz. Since the rising edge of PFS occurs a little bit before the rising edge of PDC i.e. the set-up and ...

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Table 13 shows the function taken on by each of the PCM interface pins, depending on the PCM mode and the values programmed to AIS1 and AIS0. Table 13 PCM Port 0 Mode RxD0 TxD0 TSC0 0 IN0 OUT0 TSC0 ...

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PCM Input Comparison PMOD:AIC1 … AIC0 If the PCM input comparison is enabled, the EPIC checks the contents of two PCM receive lines (physical ports) against each other for mismatches. (Also refer to chapter 5.8.2). The comparison function is operational ...

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PCM Test Loop OMDR:PTL The PCM test loop function can be used for diagnostic purposes if desired. If however a “simple” CFI to CFI connection (CFI recommended to program the PCM loop in the control memory (refer to chapter 5.4.3.1). ...

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Configurable Interface Configuration 5.2.2.1 CFI Interface Signals The configurable interface signals are summarized in the table below: Table 14 Pin No. Symbol I: Input O: Output 40 DD0/SIP0 O/IO 41 DD1/SIP1 O/ DD2/SIP2 O/ DD3/SIP3 ...

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CFI Mode Register 2 bit 7 CMD2 FC2 FC1 CFI Bit Number Register bit 7 CBNR CBN7 CBN6 CFI Time Slot Adjustment Register bit 7 CTAR 0 TSN6 CFI Bit Shift Register bit 7 CBSR 0 CDS2 CFI Bit Subchannel ...

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CFI Characteristics In the following the configurable interface characteristics that can be programmed in the CFI registers are explained in more detail. CFI Mode CMD1:CMD1, CMD0 The CFI mode primarily defines the actual number of CFI ports that can ...

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Important Note It should be noticed that there are some restrictions concerning the PCM to CFI data rate ratio. If the CFI data rate is chosen higher than the PCM data rate, no restrictions apply. If however the CFI data ...

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Internal Reference Clock (RCL) CMD2 : COC M DCL Only CFI Modes 0 and 3 CMD2 FC2 : ...0 FSC FC Modes 0-7 CFI Frame Sync CFI Data Rate Figure 30 EPIC ...

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CMD : CSP1, M DCL U 1 Bit Shift FSC CTAR CBSR: CDS2...0 CFI Frame Sync CFI Data Rate Figure 31 ® EPIC Clock Sources for the CFI and PCM Interfaces if CMD1:CSS = 1 ...

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Figure 32 shows the relationship between the DCL input and the generated RCL for the different prescaler divisors in case CMD1:CSS = 1: FSC FSC DCL RCL RCL RCL RCL RCL RCL Figure 32 Clock Signal Timing for the Different ...

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Figure 33 shows the relationship between the PFS, PDC, RCL and DCL signals in the different CFI modes. PFS PFS PDC RCL RCL DCL DCL DCL RCL RCL DCL DCL DCL RCL RCL DCL DCL DCL Figure 33 Clock Signal ...

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CFI Framing Signal Output Control CMD2:FC2 … 0 This feature applies only if the configurable interface is clocked and synchronized via the PCM interface clock and framing signals (PDC, PFS), i.e. if CMD1:CSS = 0. In this case the EPIC ...

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Figure 34 and figure 35 show the position of the FSC pulse relative to the CFI frame: Last Time-Slot of a Frame CFI Frame RCL DCL DCL DCL FSC FSC FSC FSC FSC Figure 34 Position of the FSC Signal ...

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Application Examples of the Different FC Modes FC Mode 0 FC mode 0 applies for IOM-1 multiplexed mode applications, i.e. for IOM-1 interfaces with 2.048 Mbit/s data rate. Accommodated layer-1 devices: SBC (PEB 2080), IBC (PEB 2095), IEC-T (PEB 20901/20902), ...

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FC Mode 3 FC mode 3 can be used for IOM-2 applications, but it should be noted that some IOM-2 layer-1 transceivers will interpret an FSC pulse of only one DCL period as a superframe marker (e.g. SBCX PEB 2081, ...

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Required register setting for IOM-2: CMD1 = 0XXX0000 , CMD2 = D0 B Figure 37 shows the relationship between FSC, DCL, DD# and DU#: FSC DCL DD# TS31, Bit 0 TS0,Bit 7 DU# TS31, Bit 1 TS31, Bit 0 TS0,Bit ...

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FC Mode 7 FC mode 7 is intended for IOM-2 line cards to synchronize the multiframe structure among several -interface transceivers. The layer-1 multiframe is reset by an FSC k pulse having a width of at most, ...

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CFI Bit Number CMD2, CBNR:CBN9 … CBN0 The CFI data rate is determined by the reference clock RCL and the CFI mode selected by CMD1:CMD1 … 0. The number of bits which constitute a CFI frame can be derived from ...

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DCL. Figure 40 gives a suggestion of how to adapt the external timing SYNC CLR K CLK DIN DOUT CLK ...

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CFI Bit Timing and Bit Shift CMD2, CTAR, CBSR The position of the CFI frame can be shifted relative to the CFI frame synchronization pulse using the CFI Time slot Adjustment Register CTAR and the CFI Bit Shift Register CBSR. ...

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CFI Time Slot Adjustment and Bit Shift If CBSR = 20 , the CFI framing signal (PFS if CMD1:CSS = 0 or FSC if CMD1:CSS = 1) H marks bit 7 of the CFI time slot called TSN according to ...

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DD# DU# DU# DU# TS0, Bit 7 DU# TS0, Bit 7 TS0, Bit 6 DU# TS0, Bit 7 TS0, Bit 6 TS0, Bit 5 TS0, Bit 4 TS0, Bit 3 TS0, Bit 2 TS0, Bit 1 TS0, Bit 0 DU# ...

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CFI Bit Timing In CFI modes 0, 1 and 2, the rising or falling CRCL clock edge can be selected for transmitting and sampling the data. In CFI mode 3, the rising or falling CRCL clock edge can be selected ...

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PFS PFS RCL RCL DD# DD# DU# DU# DD# DD# DU# DU# SIP# (OUT) SIP# (OUT) SIP# (IN) FSC Figure 42 CFI Bit Timing with Respect to the Framing Signal PFS (CMD1:CSS = 0) Semiconductor Group TS0, TS0, TS0, TS0, ...

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PFS PFS RCL RCL DD# DD# DU# DU# DD# DD# DU# DU# SIP# (OUT) SIP# (OUT) SIP# (IN) Figure 43 CFI Bit Timing with Respect to the Framing Signal FSC (CMD1:CSS = 1) Semiconductor Group TS0, TS0, TS0, TS0, TS0, ...

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Examples 1) In CFI mode 0, with a frame consisting of 32 time slots, the following timing relationship between the framing signal source PFS and the data signals is required: 1 PFS 0 PDC/ CRCL DD# TS31, Bit 2 DU# ...

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The CBSR:CUS bits must therefore be set to “0100”, according to figure 41. The complete value for CBSR is: CBSR = 04 Finally, the CMD2 register bits must be set to FC2 … 011, COC = 0, CXF ...

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From this it follows that: CTAR:TSN6 … TSN + The upstream CFI frame shall be shifted by 28 bits to the right (ts 4, bit bits yields in ...

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Table 19 shows the function taken over by each of the CFI interface pins, depending on the CFI mode and the values programmed to CIS1 and CIS0. Table 19 CFI Port 0 Mode DU0 DD0 0 IN0 OUT0 1 IN0 ...

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CFI subtime Slot Position CSCR If a time slot assignment is programmed in the control memory (CM), the used control memory code defines the channel bandwidth and the subchannel position at the PCM interface (refer to chapter 5.4.2). The subchannel ...

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Since for each CFI time slot there is only one control memory location, only one subchannel may be mapped to each CFI time slot. The remaining bits of such a partly unused CFI time slot are inactive e.g. set to ...

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Data and Control Memories 5.3.1 Memory Structure The EPIC memory is composed of the Control Memory (CM) and the Data Memory (DM). Their structure is shown in figure 47. The control memory refers to the Configurable Interface (CFI) such ...

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Control Memory CFI Frame Code Field 0 Up- stream 127 0 Down- stream 127 Figure 47 ® EPIC Memory Structure 5.3.2 Indirect Register Access The control and data memories must be accessed by the P in order to initialize the ...

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Memory Access Data Register bit 7 MADR MD7 MD6 The Memory Access Data Register MADR contains the data to be transferred from memory location. The meaning and the structure of this data depends on the kind of ...

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CFI Mode 0 PCM Mode 0 4 Duplex Ports 32 Tume-Slots/Port CFI Mode 1 2 Duplex Ports 64 Time-Slots/Port PCM Mode 1 2 Duplex Ports 64 Time-Slots/Port CFI Mode 2 PCM Mode 2 1 Duplex Port 128 Time-Slots/Port CFI Mode ...

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Since memory operations must be synchronized to the EPIC internal bus which is clocked by the reference clock (RCL), the time required for an indirect register access can be given as a multiple of RCL clock cycles. A “normal” access ...

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Memory Access Commands The memory access commands can be divided into the following four categories: – Access to the Data Memory Data Field: P access to PCM frame – Access to the Data Memory Code Field: PCM tristate control ...

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The Procedure for Writing to the Upstream DM Data Field is W:MADR = value to be transmitted in the PCM (sub)time slot W:MAAR = address of the desired (upstream) figure 48 bit 7 W:MACR = 0 MOC3 MOC3 … 0 ...

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MAAR: U/D MA6 . . . . Figure 49 Access to the Data Memory Data Field Semiconductor Group Data Memory Data Field U U MA0 MADR: MD7 . . . . 137 Application Hints PCM ...

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Examples In PCM mode 0 the idle code “1010 0101 W:MADR = 1010 0101 W:MAAR = 1100 0000 W:MACR = 0000 1000 The idle code can, of course, only be transmitted on the TxD# line if the corresponding tristate bits ...

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Access to the Data Memory Code (Tristate) Field The data memory code field exists only for the upstream DM block and is also called the PCM tristate field. Each (sub)time slot of each PCM transmit port can be individually ...

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The MADR bits MD7 … MD0 control the PCM time slot bit positions 7 … the following way: MD7 … MD4 are not used (don’t care); MD3 … MD0 select between the states high impedance (MD ...

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Figure 51 illustrates the access to the tristate field: MAAR: U/D MA6 . . . . . Figure 51 Access to the Data Memory Code (Tristate) Field Examples All PCM time slots shall be set to high impedance (disabled): W:MADR ...

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For test purposes this setting shall be read back: W:MAAR = 1010 1010 W:MACR = 1110 0000 wait for STAR:MAC = 0 R:MADR = XXXX 1001 5.3.3.3 Access to the Control Memory Data Field Writing to or reading the control ...

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Figure 52 illustrates this behavior. CFI Frame 0 Up- stream 127 0 Down- stream 127 MAAR: U/D MA6 . . . . Figure 52 Access to the Control Memory Data Field Semiconductor Group Control Memory Data Field U ...

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Examples In CFI mode 2, CFI time slot 123 has been initialized as a switched channel. The CM data field value therefore represents a pointer to the PCM interface first step, the involved upstream and downstream PCM time ...

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Figure 53 illustrates this behavior. CFI Frame Code Field 0 Up- stream 127 0 Down- stream 127 MACR CMC 3 Figure 53 Write Access to the Control Memory Data and Code Fields For reading back the ...

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The Procedure for Reading the CM Code is W:MAAR = CFI time slot address encoded according to figure 48 W:MACR = 1111 XXXX wait for STAR:MAC = 0 bit 7 R:MADR = X CMC3 … code, refer to ...

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Table 24 shows all available Control Memory codes. Table 24 Application CMC3 … 0 Disable connection 0000 Switched 8 bit channel 0001 Switched 4 bit channel 0011 Switched 4 bit channel 0010 Switched 2 bit channel 0111 Switched 2 bit ...

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Tristate Behavior at the Configurable Interface The downstream control memory code field, together with the CSCR and OMDR registers also defines the state of the output driver at the downstream CFI ports. Unassigned channels (code “0000”) are set to the ...

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Table 26 Summary of Memory Operations Application Writing a PCM idle value to the upstream DM data field The MACR value specifies the bandwidth and bit position at the PCM interface Reading the up- or downstream DM data field Writing ...

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Table 26 Summary of Memory Operations Application Reading the CM data field 8 bit value Reading the CM code field 4 bit code contained in Writing a switching code to the CM The MACR value specifies the bandwidth and bit ...

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Switched Channels This chapter treats the switching functions between the CFI and PCM interfaces which are programmed exclusively in the control memory. The switching functions of channels which involve the P interface or which are programmed in the synchronous ...

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CFI - PCM Time Slot Assignment All time slot assignments are programmed in the ...

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Programming kbit/s CFI - PCM Time Slot Connection – in case the CM code field has not yet been initialized with a switching code: W:MADR = PCM port and time slot encoded according to figure 48 W:MAAR ...

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Examples In PCM mode 1 and CFI mode 3 the following connections shall be programmed: Upstream: CFI port 5, time slot 7, bits 7 … PCM port 0, time slot 12, bits 7 … 0 W:MADR = 1001 ...

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After these three programming steps, the EPIC memories will have the following contents: CFI Frame Code Field 0 Up- P5, TS7 stream 127 0 P4, TS2 Down- stream 127 Figure 56 Memory Content ...

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Subchannel Switching The switching of subchannels is programmed by first specifying the time slot (which is always 8 bits wide switched, then by restricting the actual switching operation to the desired bandwidth and subtime slot position. The ...

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Subchannel selection SC#1 … SC#0 = 00: CM code CFI subchannel position CFI time slot 0001 0011 0010 0111 7 6 0110 7 6 0101 7 6 0100 7 6 Subchannel ...

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Subchannel selection SC#1 … SC#0 = 10: CM code CFI subchannel position CFI time slot 0001 0011 0010 0111 0110 0101 0100 Subchannel selection SC#1 … SC#0 = 11: CM code ...

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Examples In PCM mode 0 and CFI mode 0 the following connections shall be programmed: Upstream: CFI port 0, time slot 3, bits 1 … PCM port 0, time slot 4, bits 1 … 0 W:MADR = 1001 ...

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Downstream: CFI port 2, time slot 10, bits 5 … 4 from PCM port 0, time slot 4, bits 7 … 6 W:MADR = 0001 0000 W:MAAR = 0010 1100 W:MACR = 0111 0111 Finally the CSCR register has to ...

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Loops Loops between time slots (or even subtime slots) of the CFI (CFI interface (PCM PCM) can easily be programmed in the control memory thus possible to establish individual loops for individual time slots on both interfaces ...

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Example In PCM mode 0 and CFI mode 0 the following non-transparent CFI to CFI loop via PCM port 0, time slot 0 shall be programmed: Upstream: CFI port 2, time slot 4, bits 7 … PCM port ...

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After these three programming steps, the EPIC memories will have the following contents: CFI Frame Code Field 0 P2, TS4 Up- stream 127 0 Down- stream P1, TS7 127 Figure 58 Memory Content ...

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PCM - PCM Loops For looping back a time slot of a PCM input port to a PCM output port, two connections must be programmed: The first connection switches the downstream PCM time slot to a spare CFI time ...

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Upstream: CFI port 1, time slot 4, bits 7 … PCM port 0, time slot 5, bits 7 … 0 W:MADR = 0000 1001 W:MAAR = 1001 0010 W:MACR = 0111 0001 The following sequence sets transmit time ...

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Switching Delays When a channel is switched from an input time slot (e.g. from the PCM interface output time slot (e.g. to the CFI sometimes useful to know the frame delay introduced by this connection. ...

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The exact respective time slot positions where the delay skips from 0 frames to 1 frame and from 1 frame to 2 frames can be determined when having a closer look at the internal read and write cycles to the ...

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No Bit Shift at PCM and CFI Interface TS0 TS1 TS2 TS3 TS4 TS120 ...123 TS124 ... 127 Write Cycles RXD3 RXD3 TS0 TS1 TS60 ... 63 TS60... 63 Write Cycles RXD1 RXD3 TS0 TS30 ... 31 TS30 ... 31 ...

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No Bit Shift at PCM and CFI Interface TS0 TS1 TS2 TS3 TS4 TS30 TS31 TS0 TS1 TS2 TS3 to DU0 to DU0 to DU0 TS0 TS1 TS2 TS30 TS31 TS30 TS31 TS0 TS1 to DU0 to DU1 to DU0 ...

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How to Determine the Delay In order to determine the switching delay for a certain configuration, the following rules have to be applied with respect to the timing diagram: Data Downstream – At the PCM interface the incoming data ...

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Data Upstream – At the CFI interface the incoming data (data upstream) is written to the RAM starting with DU0 at the beginning of: time slot: 2 time slot: 2 time slot: 2 Note integer number; the ...

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Considering a Bit Shift A bit shift will also influence switching delays. If the PCM frame is shifted relative to the frame signal, proceed as indicated below: Shift only the PCM part of the figure (‘PCM line’ with the time ...

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Figure 63 Calculation of Downstream Switching Delay Semiconductor Group 173 PEB 2055 PEF 2055 Application Hints ...

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Figure 64 Calculation of Upstream Switching Delay Semiconductor Group 174 PEB 2055 PEF 2055 Application Hints ...

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Preprocessed Channels The configurable interface (CFI first sight a time slot oriented serial interface similar to the PCM interface: a CFI frame contains a number of time slots which can be switched to the PCM interface. But ...

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Initialization of Preprocessed Channels The initialization of preprocessed channels is usually performed after the CM reset sequence during device initalization. Resetting the CM sets all CFI time slots to unassigned channels (CM code ‘0000’). The initialization of preprocessed channels ...

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CFI frame is different from the value of the previous frame i.e. after at most 125 s. To initialize two consecutive CFI time slots for the decentral D Channel handling scheme, the CM ...

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After these programming steps, the control memory will have the following content: CFI Frame Up- stream Down- stream Figure 65 Control Memory Contents for Decentral D-Channel Handling Central D-Channel Handling Scheme This option applies for IOM channels where the even ...

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MR and MX bit positions can then, if required, be accessed together with the 4 bit C/I field via the even control memory address. The D-Channel can be switched kbit/s channel to and from ...

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Application hints the D channel is idle and required to transmit a 2 bit idle code in the D channel (e.g. during the layer-1 activation or for testing purposes), the 6 bit signaling handling scheme ...

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W:MADR = 1010 0100 W:MAAR = 1010 1011 W:MACR = 0111 0101 W:MADR = 0000 0010 W:MAAR = 1010 0100 W:MACR = 0110 0000 After these programming steps, the EPIC memory will have the following contents: CFI Frame Code Field ...

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Signaling Channel Scheme This option is intended for IOM channels where the even time slot consists bit monitor channel and the odd time slot bit signaling channel followed by the 2 monitor handshake ...

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Example In CFI mode 0, time slots 2 and 3 of port 0 shall be initialized for 6 bit signaling channel handling: W:MADR = 0100 0111 W:MAAR = 0000 1000 W:MACR = 0111 1010 W:MADR = XXXX XXXX W:MAAR = ...

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After these programming steps, the EPIC memory will have the following contents: CFI Frame Up- 0 stream P0, TS2 P0, TS3 127 Down- 0 stream P0, TS2 P0, TS3 127 Figure 67 Control Memory Contents for 6-Bit Signaling Channel Handling ...

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Signaling Scheme This option is intended for SLD channels where the even time slot consists bit feature control channel and the odd time slot bit signaling channel. The feature control channel is handled ...

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Summary of “Preprocessed Channel” Codes Even Control Memory Address MAAR = 0......0 DD Application Code Field Data Field MACR = 0111... MADR Decentral D Channel Handling Central D Channel ...

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Control/Signaling (CS) Handler If the configurable interface (CFI) of the EPIC is operated as IOM or SLD interface necessary to communicate with the connected subscriber circuits such as layer-1 transceivers (ISDN line cards) or codec filter devices ...

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Registers used in Conjunction with the CS Handler In detail, the following register bits are used in conjunction with the CS handler: Signaling FIFO bit 7 CIFIFO SBV SAD6 The 9 byte deep CIFIFO stores the addresses of CFI ...

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TVAL6 … 0: Timer Value bits 6 … 0; the timer period, equal TVAL6 … 0) 250 adjusted within the range of 250 ms. The timer is started as soon as CMDR:ST is ...

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Interrupt Status Register bit 7 ISTA TIN SFI The ISTA register should be read after an interrupt in order to determine the interrupt source. In connection with the signaling handler one maskable (MASK) interrupt bit is provided by the EPIC ...

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The value written to MADR should have the following format: 4 bit C/I value: MADR = bit SIG value: MADR = bit ...

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The stable value is then only updated if both new values are identical and differ from the old stored value. ...

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If the expected value “011101” is actually received upon activation of the CFI (e.g. OMDR = interrupt will be generated at this moment. But the change detection H is now enabled and each valid change in the ...

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IOM ® -1 Interface Protocol In this case the monitor channel protocol is a non handshake procedure which can be used to exchange one byte of information at a time between the EPIC and a layer-1 device such as the ...

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In IOM-2 applications, however, (active handshake protocol also possible that a slave device requests a data transfer e.g. when an IEC-Q device has received an EOC message over the U interface. For these applications the EPIC has implemented ...

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MF Channel Subscriber Address Register bit 7 MFSAR: MFTC1 MFTC0 The exchange of monitor data normally takes place with only one subscriber circuit at a time. This register serves to point the MF handler to that particular CFI time slot. ...

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Example In CFI mode 0, IOM channel 5 (time slot 16 … 19) of port 2 shall be addressed for a transmit monitor transfer: MFSAR = 0010 0110 ; the monitor channel occupies time slot 18 (10010 B (10 ) ...

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MFAIR and an ISTA:MAC interrupt is generated. The search is stopped when an active MF channel has been found or when OMDR:OMS0 is set to 0. MFFR: MFFIFO Reset; setting this bit resets the ...

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Status Register bit 7 STAR MAC TAC The status register STAR displays the current state of the MFFIFO and of the monitor transfer operation. It should be interrogated after an ISTA:MFFI interrupt and prior to accessing the MFFIFO. The STAR ...

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Description of the MF Channel Commands Transmit Command The transmit command can be used for sending MF data to a single subscriber circuit when no answer is expected applicable for both handshake and non handshake protocols. The ...

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