LSI53C1010R LSI Computer Systems, Inc., LSI53C1010R Datasheet
LSI53C1010R
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LSI53C1010R Summary of contents
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... TECHNICAL MANUAL LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller Version 2 ® S14053.A ...
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... LSI Logic officer is prohibited. Document DB14-000153-03, Third Edition (Mary 2001) This document describes the LSI Logic LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...
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... Preface This book is the primary reference and technical manual for the LSI Logic LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller. It contains a complete functional description for the product and includes complete physical and electrical specifications. Audience This document was prepared for system designers and programmers who are using this device to design an Ultra160 SCSI port for PCI-based personal computers, workstations, servers or embedded applications ...
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... Appendix B, External Memory Interface Diagram contains several example interface drawings for connecting the LSI53C1010R to external ROMs. Related Publications For background please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U ...
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SCSI SCRIPTS™ Processors Programming Guide, Order Number S14044.A LSI Logic Internet Anonymous FTP Site ftp.lsil.com (204.131.200.1) Directory: /pub/symchips/scsi PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in ...
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Preface ...
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... Contents Chapter 1 Introduction 1.1 General Description 1.2 Benefits of Ultra160 SCSI 1.3 Benefits of SURElink (Ultra160 SCSI Domain Validation) 1.4 Benefits of LVD Link™ 1.5 Benefits of TolerANT 1.6 Summary of LSI53C1010R Benefits 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 Chapter 2 Functional Description 2.1 PCI Functional Description 2.1.1 2.1.2 2.1.3 2.1.4 2.2 SCSI Functional Description 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 Contents ® Technology SCSI Performance ...
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... Parallel ROM Interface 2.4 Serial EEPROM Interface 2.4.1 2.4.2 2.5 Power Management 2.5.1 2.5.2 2.5.3 2.5.4 Chapter 3 Signal Descriptions 3.1 Signal Organization 3.2 Internal Pull-ups and Pull-downs on LSI53C1010R Signals 3.3 PCI Bus Interface Signals 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 SCSI Bus Interface Signals 3.4.1 3.4.2 3.5 General Purpose I/O (GPIO) Signals 3.6 Flash ROM and Memory Interface Signals 3.7 Test Interface Signals viii ...
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Power and Ground Signals 3.9 MAD Bus Programming Chapter 4 Registers 4.1 PCI Configuration Registers 4.2 SCSI Registers 4.3 SCSI Shadow Registers Chapter 5 SCSI SCRIPTS Instruction Set 5.1 SCSI SCRIPTS 5.1.1 5.2 Block Move Instructions 5.2.1 5.2.2 5.2.3 ...
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... DMA FIFO Sections 2.3 LSI53C1010R Host Interface SCSI Data Paths 2.4 Regulated Termination for Ultra160 SCSI 2.5 Determining the Synchronous Transfer Rate 2.6 Interrupt Routing Hardware Using the LSI53C1010R 2.7 Block Move and Chained Block Move Instructions 3.1 LSI53C1010R Functional Signal Grouping 4.1 Single Transition Transfer Waveforms 4.2 Double Transition Transfer Waveforms (XCLKS Examples) 4 ...
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SCRIPTS Overview 5.2 Block Move Instruction - First Dword 5.3 Block Move Instruction - Second Dword 5.4 Block Move Instruction - Third Dword 5.5 First 32 bit Word of the I/O Instruction 5.6 Second 32-Bit Word of the I/O ...
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... Target Asynchronous Send 6.38 Target Asynchronous Receive 6.39 Initiator and Target ST Synchronous Transfer 6.40 Initiator and Target DT Synchronous Transfer 6.41 LSI53C1010R 456 BGA Chip - Top View 6.42 LSI53C1010R 456 BGA Mechanical Drawing B.1 16 Kbyte Interface with 200 ns Memory B.2 64 Kbyte Interface with 150 ns Memory B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory B ...
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... Default Download Mode Serial EEPROM Data Format 2.9 Power States 3.1 LSI53C1010R Internal Pull-ups and Pull-downs 3.2 System Signals 3.3 Address and Data Signals 3.4 Interface Control Signals 3.5 Arbitration Signals 3.6 Error Reporting Signals 3.7 Interrupt Signals 3.8 SCSI Bus Interface Signal 3.9 SCSI Function A Signals 3.10 SCSI Function A Control Signals 3 ...
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Bidirectional Signals – MAD[7:0] 6 Output Signals – MAS[1:0]/, MCE/, MOE/_TESTOUT, MWE/, TDO 6. PCI Bidirectional Signals – AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/ 6.11 Input Signals ...
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... Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6.50 Ultra160 SCSI Transfers 160 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6.51 Alphanumeric List by BGA Position 6.52 Alphanumeric List by Signal Name A.1 LSI53C1010R PCI Register Map A.2 LSI53C1010R SCSI Register Map Contents 6-61 6-62 6-63 6-63 6-64 6-64 6-65 6-65 6-66 6-67 6-67 6-68 ...
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Contents ...
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... Chapter 1 Introduction This chapter provides a general overview of the LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller. This chapter contains the following sections: Section 1.1, “General Description” Section 1.2, “Benefits of Ultra160 SCSI” Section 1.3, “Benefits of SURElink (Ultra160 SCSI Domain Validation)” ...
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... SCSI transfer rate to optimize interoperability. Three levels of Domain Validation are provided, assuring robust system operation. The LSI53C1010R has a local memory bus. This allows local storage of the device’s BIOS ROM in flash memory or standard EPROMs. The LSI53C1010R supports programming of local flash memory for BIOS updates ...
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... Typical PCI Computer System Architecture The LSI53C1010R is pin compatible with the LSI53C1030 PCI to Dual Channel Ultra320 SCSI Multifunction Controller. Proper board design, using LSI Logic Design Considerations for the LSI53C1010R and LSI53C1030, SEN S11019, allows seamless, low risk upgrade from the Ultra160 LSI53C1010R to the Ultra320 LSI53C1030. 1.2 Benefi ...
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... CRC-32. CRC is guaranteed to detect all single bit errors, any two bits in error, or any combination of errors within a single 32-bit range. AIP is also supported by the LSI53C1010R, protecting all nondata phases, including command, status, and messages. CRC, along with AIP, provides end-to-end protection of the SCSI I/O. ...
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... Benefits of LVD Link™ The LSI53C1010R supports LVD through LVD Link. This signaling technology increases the reliability of SCSI data transfers over longer distances than are supported by SE SCSI. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip ...
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... SCSI operations. TolerANT input signal filtering is a built-in feature of the LSI53C1010R and all LSI Logic Fast, Ultra, Ultra2, and Ultra160 SCSI devices. The benefits of TolerANT technology include increased noise immunity when the signal transitions to HIGH, better performance due to balanced duty cycles, and improved fast SCSI transfer rates ...
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... Summary of LSI53C1010R Benefits This section provides a summary of the LSI53C1010R features and benefits. It contains information on SCSI Performance, PCI Performance, Integration, Ease of Use, Flexibility, Reliability, and Testability. 1.6.1 SCSI Performance The LSI53C1010R: Performs wide, Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s on each SCSI channel for a total of 320 Mbytes/s using DT clocking ...
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... Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast I/O context switching. Supports expanded Register Move instruction to support additional arithmetic capability. 1.6.2 PCI Performance The LSI53C1010R: Complies with PCI 2.2 specification. Supports a 64-bit/66 MHz PCI interface for 528 Mbytes/s bandwidth that: – – ...
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... Integrated SCRIPTS processor. 1.6.4 Ease of Use The following features of the LSI53C1010R make the device user friendly. The LSI53C1010R is pin compatible with the LSI53C1030 PCI to Dual Channel Ultra320 SCSI Multifunction Controller. Summary of LSI53C1010R Benefits Supports dual address cycle (DAC) generation for all SCRIPTS ...
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... Software for PC-based operating system support. Support for relative jumps. SCSI Selected As ID bits for responding with multiple IDs. 1.6.5 Flexibility The following features increase the flexibility of the LSI53C1010R: Universal LVD transceivers are backward compatible with SE devices. High level programming interface (SCSI SCRIPTS). ...
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... Selectable IRQ pin disable bit. Compatible with 3.3 V and 5 V PCI. 1.6.6 Reliability The following features enhance the reliability of the LSI53C1010R: CRC and AIP provide end-to-end SCSI I/O protection ESD protection on SCSI signals. Protection against bus reflections due to impedance mismatches. Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certifi ...
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Introduction ...
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... Chapter 2 Functional Description This chapter provides a functional description of the LSI53C1010R. This chapter is divided into the following sections: Section 2.1, “PCI Functional Description” Section 2.2, “SCSI Functional Description” Section 2.3, “Parallel ROM Interface” Section 2.4, “Serial EEPROM Interface” Section 2.5, “Power Management” ...
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... SCSI Function A Bus Wide Ultra160 SCSI Bus The LSI53C1010R has two wide Ultra160 SCSI channels in a single package. Each SCSI channel (A and B) incorporates an independent DMA FIFO and a separate internal 8 Kbyte SCRIPTS RAM. 2.1 PCI Functional Description The LSI53C1010R implements two PCI to Wide Ultra160 SCSI controllers in a single package. This confi ...
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... PCI Configuration Register Map. At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the LSI53C1010R, the upper 24 bits of the address are selected. On every access, the LSI53C1010R compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If the upper 24 bits match, the access is designated for the LSI53C1010R. The low order eight bits defi ...
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... I/O Space The PCI specification defines I/O space as a contiguous 32-bit I/O address that is shared by all system resources, including the LSI53C1010R. which 256-byte I/O area this device occupies. 2.1.1.3 Memory Space The PCI specification defines memory space as a contiguous 64-bit memory address that is shared by all system resources. ...
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... See the 2. See the 2.1.2.1 Interrupt Acknowledge Command The LSI53C1010R does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 Special Cycle Command The LSI53C1010R does not respond to this command as a slave and it never generates this command as a master. ...
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... Memory Address Space. The target may perform an anticipatory read if such a read produces no side effects. 2.1.2.7 Memory Write Command The LSI53C1010R uses the Memory Write command to write data to an agent mapped in the Memory Address Space. When the target returns “ready”, it assumes responsibility for data coherency, which includes ordering. 2.1.2.8 Confi ...
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... The maximum allowable burst size is determined from the (DMODE) 2.1.2.11 Dual Address Cycles (DACs) Command When 64-bit addressing is required, the LSI53C1010R performs DACs, per the PCI 2.2 specification. If any of the selector registers contain a nonzero value, a DAC is generated. PCI Functional Description ...
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... The Read Line function in the LSI53C1010R takes advantage of the PCI 2.2 specification regarding issuance of this command. If the cache mode is disabled, no Read Line commands are issued. ...
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... The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst. The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C1010R issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. ...
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... PCI bus. An internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for PCI bus access. There are two independent bus mastering functions inside the LSI53C1010R, one for each of the SCSI functions. 2-10 ...
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... PCI bus. This ensures that no function is starved for access to the PCI bus. 2.1.4 PCI Cache Mode The LSI53C1010R supports the PCI specification for an 8-bit Size (CLS) Line Size (CLS) nonaligned addresses corresponding to cache line boundaries. In ...
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Table 2.2 G 2.1.4.1 Enabling Cache Mode To enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any PCI master operation, the following conditions must be met: The ...
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Not only must the above four conditions be met in order for the cache logic to control the type of PCI cache command that is issued, proper alignment is also necessary during write operations. If these conditions are not met ...
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Memory Read Multiple command is issued transfer does not cross a Dword or cache boundary or if cache mode is not enabled a Memory Read command is issued. 2.1.4.4 Memory Write Caching Memory Writes are aligned ...
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MRM (16 bytes) MRM (16 bytes) MRM (16 bytes) MRM (16 bytes) MRM (16 bytes byte MRM (16 bytes) MRM (16 bytes) MRM (16 bytes) MRM (16 bytes bytes) Read ...
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Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords Write Example ...
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... If the source and destination are not quad word aligned, i.e., Source Address[2:0] == Destination Address[2:0], write alignment is not performed and Memory Write and Invalidates are not issued. The LSI53C1010R is little endian. This mode assigns the least significant byte to bits [7:0]. PCI Functional Description MW (15 bytes) ...
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... Ultra160 SCSI requirements. between the LSI53C1010R modules. The LSI53C1010R offers low level register access or a high level control interface. Like first generation SCSI devices, the LSI53C1010R is accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus is used in error recovery and diagnostic procedures ...
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... SCRIPTS instructions. These registers are described in detail in 2.2.2 Internal SCRIPTS RAM The LSI53C1010R has 8 Kbytes (2048 x 32 bits) of internal, general purpose RAM for each SCSI function. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. ...
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... Load and Store instruction memory move instruction. One of the selector registers is dynamic and is used during 64-bit direct block moves only. All selectors will default to zero, meaning the LSI53C1010R will power- state where only Single Address Cycles (SACs) are generated. When any of the selector registers are written to a nonzero value, DACs are generated ...
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... LSI53C1010R is not performing an EEPROM autodownload. The CON (Connected) bit in the LSI53C1010R is connected to the SCSI bus either as an initiator or a target. This happens after the LSI53C1010R has successfully completed a selection or when it has successfully responded to a selection or reselection. The CON bit is also set when the LSI53C1010R wins arbitration in low level mode ...
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SCSI, refer to the SCSI Parallel Interface-3 (SPI-3) working document that is available on the world wide web at the T10 Home Page, http://www.t10.org. Also, check the SCSI Trade Association web site at http://www.scsita.org/. Ultra160 SCSI timing information. In addition ...
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Data-In and DT Data-Out. The use of DT and ST phases implies that the SCRIPTS engine may use a different jump point for DT or ST. illustrates SCSI signal configuration for these phases. Table 2.3 Phase ST Data-Out ST Data-In ...
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Transfer Period Factor (Byte 3) – Transfer Period Factor is the old Synchronous Period value. These are the same with one addition for the 80 megatransfers/s rate: 0x09 0x0A 0x0B 0x0C 0x0D–0xFF The transfer period depends on the data transfer ...
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Protocol Options (Byte 7) – QAS_REQ bus or device reset, power cycle, or change between LVD/SE modes invalidates these settings. A renegotiation resets the Protocol Options. 2.2.5.3 Asynchronous Information Protection (AIP) The AIP feature ...
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... Register Considerations The following is a summary of the registers and bits required to enable Ultra160 SCSI on the LSI53C1010R device. The PCI The PCI it requires the bus every 4.5 s. The – – The – The – – – – The – – The – 2-26 Functional Description Device ID register value must be 0x21 ...
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The SCSI Interrupt Enable Zero (SIEN0) – Bit 0, PAR (SCSI Parity/CRC/AIP Error), is set to detect a parity/CRC/AIP error while receiving or sending SCSI data. For more information, see The Chip Control Three (CCNTL3) – Bit 4, ENDSKEW (Enable ...
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Note: The – – – – The – – – – – The – The – 2-28 Functional Description Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST Transfer Edge) is set to add a clock of data ...
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... Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the LSI53C1010R to not check for a CRC request prior to a phase change on the SCSI bus. This condition creates a SCSI error condition and makes the device noncompliant with the SPI-3 specification. Do not set this bit under normal operating conditions. – ...
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... Using the SCSI Clock Quadrupler The LSI53C1010R can quadruple the frequency MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is user-selectable with bit settings in the Test Three power-on or reset, the quadrupler is disabled and powered down. Follow these steps to use the clock quadrupler: 1 ...
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... To ensure the LSI53C1010R always operates from the current version of the SCRIPTS instruction, the contents of the prefetch unit may be flushed under certain conditions. The contents of the prefetch unit are automatically flushed under the following conditions: On every Memory Move instruction The Memory Move instruction is used to place modified code into memory. To assure the device executes recent modifi ...
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... Note: 2.2.8 Load and Store Instructions The LSI53C1010R supports the Load and Store instruction type, which simplifies data movement between memory and the internal registers. It also enables the chip to transfer bytes to addresses relative to the Structure Address (DSA) the SCRIPTS RAM remain internal to the chip and do not generate PCI bus cycles ...
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... SCRIPTS RAM must first be written before being read in order to initialize SCRIPTS RAM parity SCRIPTS RAM parity error is encountered, a SCSI Gross Error interrupt is signaled. The LSI53C1010R supports CRC checking and generation in DT phases and CRC checking and generation during DT Data Transfers. The new CRC registers are: Control Zero (CRCD) ...
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... Data Latch (SIDL) This bit enables parity checking during PCI master data phases. This bit is set when the LSI53C1010R PCI master, detects a target device signaling a parity error during a data phase. By clearing this bit, a Master Data Parity Error does not ...
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... SCSI Interrupt Enable One 2.2.11 DMA FIFO The DMA FIFO is 8 bytes wide by 112–115 transfers deep depending on the type and direction of data transfer. The DMA FIFO is illustrated in Figure 2.2. The small FIFO mode (112 bytes) is not supported by the LSI53C1010R. Figure 2.2 DMA FIFO Sections . . . ...
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... DMA transfers. The FIFO allows the LSI53C1010R to support 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12 SCSI Data Paths The data path through the LSI53C1010R is dependent on whether data is moved into or out of the chip and whether the SCSI data transfer is asynchronous or synchronous. ...
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If bit 5 (OLF1) in the most significant byte in the SODL register contains data. Checking these bits also reveals bytes left in the SODL register from a Chained Move operation with an odd byte count. To recover from all ...
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... There should be a means of disabling the termination. SE cables can use a 220 supply (Term Power) line and a 330 Because of the high-performance nature of the LSI53C1010R, regulated 2-38 Functional Description register, and bit 5 (previously DIF), of the register, are reserved. The A_DIFFSENS or pull-up resistor to the terminator power pull-down resistor to ground ...
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... SCSI controller (operating in the initiator mode) tries to select a target and is reselected by another. The Select SCSI Functional Description If the LSI53C1010R is used in a design with an 8-bit SCSI bus, all 16 data lines must be terminated. Regulated Termination for Ultra160 SCSI Line9 ...
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... Set Initiator instruction or the target SCRIPTS issues a Set Target instruction. The Selection and Reselection Enable bits ID (SCID) the LSI53C1010R to respond as an initiator target. If only selection is enabled, the LSI53C1010R cannot be reselected as an initiator. Status bits, in the and interrupt bits, in the indicate if the LSI53C1010R has been selected or reselected ...
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... DT SCSI transfers on the DT edge. This bit only impacts DT transfers as it only affects data hold to the DT edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010R receives outbound REQs, ACKs, or data. SCSI Functional Description ...
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... SCSI transfers on the ST edge. This bit impacts DT and ST transfers as it affects data hold to the ST edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010R receives outbound REQs, ACKs, or data. 2.2.15.3 Determining the Data Transfer Rate ...
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... To configure the LSI53C1010R for Ultra160 DT transfers, perform the following steps: Step 1. Enable the SCSI Clock Quadrupler – The LSI53C1010R can quadruple the frequency MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is user selectable through bit settings in the register ...
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... The SCRIPTS processors in the LSI53C1010R perform most functions independently of the host microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C1010R. 2.2.16.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts ...
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... SCSI Function A is routed to PCI Interrupt INTA/. SCSI Function B is normally routed to INTB/, but can be routed to INTA pull-up is connected to MAD[4]. See additional information. 2.2.16.2 Registers The registers in the LSI53C1010R used for detecting or defining interrupts are (ISTAT1), SCSI Interrupt Status Zero (SIST1), SCSI Interrupt Enable One See the register descriptions in information ...
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... Interrupt Status Zero (SIST0) clear the CRC Error bit (bit 7) in the register. If the LSI53C1010R is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could remain in the DMA FIFO. To determine if the DMA FIFO is empty, check the DMA FIFO Empty (DFE) ...
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... SCSI Functional Description Chip Test Three (CTEST3) SCSI Test Three (STEST3) DMA Status (DSTAT) register contains the status of register. Since the LSI53C1010R DMA Status (DSTAT) SCSI Interrupt Enable Zero (SIEN0) registers are the interrupt enable registers SCSI Interrupt Status Zero (SIST0) (SIST1) ...
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... CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C1010R is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or handshake-to-handshake timers expire. These interrupts are not needed for events that occur during high level SCRIPTS operation ...
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... Interrupt Status Zero (ISTAT0) the INTA/ (or INTB/) pin. 2.2.16.5 Stacked Interrupts The LSI53C1010R stacks interrupts, if they occur, one after the other. If the SIP or DIP bits in the (first level), then there is already at least one pending interrupt. Any future interrupts are stacked in extra registers behind the ...
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... These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C1010R attempts to halt in an orderly fashion. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault. Execution does not begin, but the DSP points to the next instruction since it is updated when the current instruction is fetched ...
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... All other instructions may halt before completion. 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C1010R. It can be repeated if polling is used, or should be called when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used. 1. Read 2. If the INTF bit is set, write one to clear this status. ...
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... Interrupt Routing This section documents the recommended approach to RAID ready interrupt routing for the LSI53C1010R. In order to be compatible with RAID upgrade products and the LSI53C1010R, the following requirements must be met: When a RAID upgrade card is installed in the upgrade slot, interrupts ...
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... If this restriction is not acceptable, additional buffer logic must be implemented on the mainboard. As long as the interrupt routing requirements stated above are satisfied, a mainboard designer could implement this design with external logic. Figure 2.6 Interrupt Routing Hardware Using the LSI53C1010R LSI53C1010R 2 ...
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... PCI BIOS calls when searching for PCI devices. 2.2.18 Chained Block Moves Since the LSI53C1010R has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI ...
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Moves five bytes from address 0x03 in the host memory to the SCSI bus. Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the SCSI core (in the lower byte of the SODL register for asynchronous ...
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Chained Block Move instruction. Under this condition the high-order byte is not transferred out the DMA channel to memory. Instead stored in the Residue (SWIDE) The hardware uses ...
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... SCSI bus recommended that all Block Move instructions be Chained Block Moves. 2.3 Parallel ROM Interface The LSI53C1010R supports Mbyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add-in PCI cards. Both functions of the device share the ROM interface. ...
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... Reset signal and configures the Expansion ROM Base Address register and the memory cycle state machines for the appropriate conditions. The LSI53C1010R supports a variety of sizes and speeds of expansion ROM. An example set of interface drawings is in Memory Interface Diagram Examples.” ...
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... MAD[2]. If the external memory interface is not used, MAD[3:1] should be pulled HIGH. The LSI53C1010R allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI configuration space. For more information on how this works, refer to the PCI specifi ...
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... The Subsystem ID and Subsystem Vendor ID registers are read only, per the PCI specification, with a default value of 0x1000 and 0x1000 respectively. 2.5 Power Management The LSI53C1010R complies with the PCI Bus Power Management Interface Specification, Revision 1.1, in which the D0, D1, D2, and D3 are defined. 2-60 Functional Description The speed of the serial EEPROM must be 400 Kbits/s ...
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... Power state actions are separate for each function. 2.5.1 Power State D0 Power state D0 is the maximum power state and is the power-up default state for each function. The LSI53C1010R is fully functional in this state. 2.5.2 Power State D1 Power state lower power state than D0. A function in this state places the LSI53C1010R core in the snooze mode and disables the SCSI CLK ...
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... D0 by applying V Power state lower power level than power state D2. A function in this state places the LSI53C1010R core in the coma mode. Furthermore, the function's soft reset is continually asserted while in power state D3, which clears all pending interrupts and 3-states the SCSI bus. In ...
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... Chapter 3 Signal Descriptions This chapter describes the input and output signals of the LSI53C1010R. The chapter consists of the following sections: Section 3.1, “Signal Organization” Section 3.2, “Internal Pull-ups and Pull-downs on LSI53C1010R Signals” Section 3.3, “PCI Bus Interface Signals” Section 3.4, “SCSI Bus Interface Signals” ...
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The PCI Interface contains many functional groups of signals. The SCSI Bus Interface contains two functional groups of signals. There are five signal type definitions: I Input, a standard input-only signal. O Output, a standard output driver (typically a Totem ...
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... Figure 3.1 LSI53C1010R Functional Signal Grouping System Address and Data Interface PCI Control Bus Interface Arbitration Error Reporting Interrupt SCSI Function A GPIO SCSI Function B GPIO Flash ROM and Memory Interface Signal Organization LSI53C1010R CLK SCLK ENABLE66 M66EN RST/ A_SD[15:0] A_SDP[1:0] AD[63:0] A_DIFFSENS C_BE[7:0]/ ...
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... Internal Pull-ups and Pull-downs on LSI53C1010R Signals Several LSI53C1010R signals use internal pull-ups and pull-downs. Table 3.1 pull-downs. Table 3.1 LSI53C1010R Internal Pull-ups and Pull-downs Pull Pin Name Current INTA/, INTB/, ALT_INTA ALT_INTB/ ENABLE66, M66EN TCK_CHIP, TDI_CHIP, TEST_RST/, TMS_CHIP AD[63:32], C_BE[7:4]/, 25 A PAR64 ...
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PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, Interrupt Signals. 3.3.1 System Signals ...
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Address and Data Signals Table 3.3 Table 3.3 Address and Data Signals Name Bump AD[63:0] W22, AB25, AC26, AA25, W23, Y25, Y26, V22, U22, V24, V23, U24, V25, W26, U23, U25, T22, T23, T25, R25, R22, P22, P23, R23, ...
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Table 3.3 Address and Data Signals (Cont.) Name Bump PAR64 AA24 3.3.3 Interface Control Signals Table 3.4 Table 3.4 Interface Control Signals Name Bump Type ACK64/ AB20 S/T PCI Acknowledge 64-bit transfer is driven by the current bus ...
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Table 3.4 Interface Control Signals (Cont.) Name Bump Type STOP/ AB16 S/T PCI Stop indicates that the selected target is requesting the DEVSEL/ AC16 S/T PCI Device Select indicates that the driving device has IDSEL AC13 ...
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Error Reporting Signals Table 3.6 Table 3.6 Error Reporting Signals Name Bump Type Strength Description PERR/ AE17 S/T PCI Parity Error may be pulsed active by an agent that detects SERR/ AC17 PCI System ...
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... SCSI Test One (STEST1) information about disabling this interrupt in a RAID environment. At power-up, this interrupt can be rerouted to INTA/ using the INTA/ enable sense resistor (pull-up on MAD4). This causes the LSI53C1010R to program the SCSI Function B PCI Interrupt Pin (IP) in Chapter 4, “Registers,” ...
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SCSI Bus Interface Signals The SCSI Bus Interface Signals section contains tables describing the signals for the following signal groups: SCSI Bus Interface Signals, SCSI Function A Signals, and SCSI Function B Signals. SCSI Function A Signals and SCSI ...
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Table 3.9 SCSI Function A Signals (Cont.) Name Bump A_SDP[1:0] W2, P4 A_SDP[1:0]+ W1, P5 A_DIFFSENS E2 3-12 Signal Descriptions Type Strength Description I/O SE: SCSI Function A Parity SCSI LVD Mode: Negative half of the LVD Link ...
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Table 3.10 SCSI Function A Control Signals 1 Name Bump Type SCSI Function A Control includes the following signals: A_SCD K3 I/O A_SCD+ K4 A_SIO K5 A_SIO+ J5 A_SMSG L2 A_SMSG+ L1 A_SREQ J2 A_SREQ+ J3 A_SACK M5 A_SACK+ L5 ...
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SCSI Function B Signals This section describes the SCSI Function B Signals group. describes the SCSI Function B Signals and SCSI Function B Control Signals. Table 3.11 SCSI Function B Signals Name Bump B_SD[15:0] D8, E8, C6, A3, B21, ...
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Table 3.11 SCSI Function B Signals (Cont.) Name Bump B_DIFFSENS B22 SCSI Bus Interface Signals Type Strength Description I N/A SCSI Function B Differential Sense pin detects the present mode of the SCSI bus when connected to the DIFFSENS signal ...
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Table 3.12 SCSI Function B Control Signals 1 Name Bump Type SCSI Function B Control includes the following signals: B_SCD E16 I/O B_SCD+ D17 B_SIO E17 B_SIO+ D18 B_SMSG B16 B_SMSG+ D16 B_SREQ B18 B_SREQ+ C18 B_SACK D14 B_SACK+ E14 ...
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... MAD7 pin, to serve as the clock signal for the serial EEPROM interface. If bit 7 of the (GPCNTL) register is set, this pin drives LOW when the LSI53C1010R is the bus master SCSI Function A General Purpose I/O pin 2. This pin powers input SCSI Function A General Purpose I/O pin 3 ...
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... MAD7 pin to serve as the clock signal for the serial EEPROM interface. If bit 7 of the (GPCNTL) register is set, this pin is driven LOW when the LSI53C1010R is the bus master SCSI Function B General Purpose I/O pin 2. This pin powers input SCSI Function B General Purpose I/O pin 3 ...
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... Memory Address Strobe 1. This pin latches in the most significant address byte (bits [15:8 external EEPROM or flash memory. Since the LSI53C1010R moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops that assemble 20-bit address for the external memory ...
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Test Interface Signals Table 3.16 divided into Internal Test Signals and JTAG Signals. Table 3.16 Test Interface Signals Name Bump Internal Test Signals: SCAN_MODE E7 SCANEN N22 IDDTN Y4 TEST_HSC D7 TEST_RST/ AD5 JTAG Signals: TCK_CHIP AC6 TMS_CHIP AE4 ...
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Power and Ground Signals Table 3.17 Table 3.17 Power and Ground Signals 1 Name Bump VSS_IO A5, A9, A13, A17, A21, A25, B1, B26, C4, C8, C12, C16, C20, D24, E1, F26, G3, H24, J1, K26, L3, L11, L12, ...
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Table 3.17 Power and Ground Signals (Cont.) 1 Name Bump VSSA AB6, H5 A_VDDBIAS T1 B_VDDBIAS B13 B_RBIAS A11 NC A24, B2, B3, B23, B24, B25, C2, C3, C5, C14, C22, C24, C25, D4, D5, D15, D20, D21, D22, D23, ...
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LOW at reset or by connecting a 4.7 k resistor between the appropriate MAD[x] pin and V pull-down resistors require that HC or HCT external components are used for the memory interface. A ...
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Table 3.18 MAD[3:1] 000 001 010 011 100 101 110 111 MAD[0], slow ROM – When pulled up, this pin enables use of slower memory devices by including two extra data access cycles. Note: 3-24 Signal Descriptions MAD[3:1] Pin Decoding ...
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... Chapter 4 Registers This section contains descriptions of all LSI53C1010R registers. The term “set” refers to bits programmed to a binary one. Similarly, the term “cleared” refers to bits programmed to a binary zero. Do not access reserved bits. Reserved bit functions may change at any time. Unless otherwise indicated, all bits in the registers are active HIGH ...
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... LSI53C1010R are described in this chapter. Do not access bits marked as Reserved. Table 4.1 PCI Configuration Register Map 31 Device ID Status Class Code (CC) Reserved Header Type (HT) Base Address Register Zero (BAR0) (I/O) Base Address Register One (BAR1) (MEMORY) ...
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... The SCSI Command Register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C1010R is logically disconnected from the PCI bus for all accesses except configuration accesses. R Reserved SE SERR/Enable When this bit is set, the LSI53C1010R enables the SERR/ driver ...
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... Reserved Enable Bus Mastering This bit controls the ability of the LSI53C1010R to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1010R to behave as a bus master ...
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... DPE Detected Parity Error (from Slave) This bit is set by the LSI53C1010R upon the detection of a data parity error, even if data parity error handling is disabled. SSE Signaled System Error This bit is set whenever the device asserts the SERR/ signal ...
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... Fast Back to Back Capable This bit is zero. Reserved 66 MHz Capable When set, this bit indicates that the LSI53C1010R is capable of 66 MHz PCI operation. This bit is controlled by the ENABLE66 pin, which has a static pull-up. New Capabilities This bit is set to indicate a list of extended capabilities such as PCI Power Management ...
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Registers: 0x09–0x0B Class Code (CC) Read Only Register: 0x0C Cache Line Size (CLS) Read/Write 7 0 CLS PCI Configuration Registers Class ...
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... The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C1010R support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C1010R ...
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... Base Address Register Zero - I/O This base address register is used to map the operating register set into I/O space. The LSI53C1010R requires 256 bytes of I/O space for this base address register. Bit 0 is hardwired to one. Bit 1 is reserved and returns a zero on all reads. All other bits are used to map the device into I/O space ...
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... SCRIPTS RAM into memory space and represents the lower 32 bits of the memory address. Bits [12:0] are hardwired to 0b0000000000100. The default value of this register is 0x00000004. The LSI53C1010R requires 8192 bytes of memory space for SCRIPTS RAM. For detailed information on the operation of this register, refer to the PCI 2.2 specification. 0 ...
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... SCRIPTS RAM into memory space and represents the upper 32 bits of the memory address. The default value of this register is 0x00000000. The LSI53C1010R requires 8192 bytes of memory space for SCRIPTS RAM. For detailed information on the operation of this register, refer to the PCI 2.2 specification. ...
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Registers: 0x2C–0x2D Subsystem Vendor ID (SVID) Read Only SVID 4-12 Registers SVID If MAD7 is HIGH MAD7 is LOW Subsystem ...
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Registers: 0x2E–0x2F Subsystem ID (SID) Read Only SID Subsystem ID This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device ...
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... Expansion ROM Base Address (ERBA) ones and then reading back the register. The SCSI functions of the LSI53C1010R respond with zeros in all don’t care locations. The least significant one (1) that remains represents the binary version of the external memory size ...
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Register: 0x34 Capabilities Pointer (CP) Read Only Registers: 0x35–0x37 Reserved This register is reserved. Registers: 0x38–0x3B Reserved This register is reserved. PCI ...
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Register: 0x3C Interrupt Line (IL) Read/Write Register: 0x3D Interrupt Pin (IP) Read Only Note: 4-16 Registers Interrupt Line This register is used to communicate interrupt line routing ...
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... Min_Gnt This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 s. The LSI53C1010R sets this register to 0x11. Register: 0x3F Max_Lat (ML) ...
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... D2S D1S AUX_C PME_Support Bits [15:11] define the power management states in which the LSI53C1010R will assert the PME pin. These bits are all set to zero because the LSI53C1010R does not provide a PME signal [7: [7:0] ...
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... R Reserved PMEC PME Clock Bit 3 is cleared because the LSI53C1010R does not provide a PME pin. VER[2:0] Version These three bits are set to 0b010 to indicate that the LSI53C1010R complies with Revision 1.1 of the PCI Power Management Interface Specifi ...
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... The LSI53C1010R always returns zero for this bit to indicate that PME assertion is disabled. Reserved Power State Bits [1:0] are used to determine the current power state of the LSI53C1010R. They are used to place the LSI53C1010R in a new power state. Power states are defined as: 0b00 D0 0b01 D1 0b10 D2 0b11 D3 hot See Section 2.5, “ ...
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... Register: 0x47 Data Read Only DATA Data This register provides an optional mechanism for the function to report state-dependent operating data. The LSI53C1010R always returns 0x00. PCI Configuration Registers DATA [7:0] 4-21 ...
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... Updated Address (UA), (IA), SCSI Byte Count registers. All of the phase The only registers that the host CPU can access while the LSI53C1010R is executing SCRIPTS are the tus Zero (ISTAT0), Interrupt Status One Zero (MBOX0), and Mailbox One (MBOX1) attempts to access other registers interfere with the operation of the chip ...
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Table 4.2 SCSI Register Map 31 16 SCNTL3 SCNTL2 GPREG SDID SBCL SSID SSTAT2 SSTAT1 MBOX1 MBOX0 CTEST3 CTEST2 CTEST6 CTEST5 DCMD DCNTL SBR SIST1 SIST0 GPCNTL Reserved RESPID1 RESPID0 STEST3 STEST2 CSO STEST4 CCNTL1 CCNTL0 CCNTL3 CCNTL2 SCRATCH C–SCRATCH ...
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... Full arbitration, selection/reselection Simple Arbitration 1. The LSI53C1010R SCSI function waits for a bus free condition to occur asserts SBSY/ and its SCSI ID, contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI device, the LSI53C1010R SCSI function deasserts SBSY/, deasserts its ID, and sets the Lost Arbitration ...
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... Full Arbitration, Selection/Reselection 1. The LSI53C1010R SCSI function waits for a bus free condition asserts SBSY/ and its SCSI ID onto the SCSI bus. The SCSI ID asserted is the highest priority ID stored in the 3. If the SSEL/ signal is asserted by another SCSI device or if the LSI53C1010R SCSI function detects ...
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... Registers the arbitration sequence is complete sequence is aborted, check bit 4 in the SCNTL1 register to verify that the LSI53C1010R is not connected to the SCSI bus. Select with SATN Start Sequence When this bit is set and the SCSI function is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device ...
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... This is done using the SCRIPTS language (SET TARGET or CLEAR TARGET). When this bit is set, the chip is a target device. When this bit is cleared, the LSI53C1010R SCSI function is an initiator device. Caution: Writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes ...
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... If the LSI53C1010R SCSI function is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C1010R SCSI function does not halt the SCSI transfer when SATN Parity/CRC/AIP error is received. 3 ...
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... Connected This bit is automatically set any time the LSI53C1010R SCSI function is connected to the SCSI bus as an initiator target set after the LSI53C1010R SCSI function successfully completes arbitration or when it has responded to a bus initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode ...
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... SCSI bus not acceptable the Bus Free phase immediately following the arbitration phase possible to perform a low level selection instead. The abort completes because the LSI53C1010R SCSI function loses arbitration. This is detected by the clearing of the Immediate Arbitration bit. Do not use the Lost Arbitration bit bit 3) to detect this condition ...
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To SCSI Control Two expects a disconnect to occur, normally prior to sending an Abort, Abort Tag, Bus Device Reset, Clear Queue or Release Recovery message, or before deasserting SACK/ after ...
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WSR Register: 0x03 SCSI Control Three (SCNTL3) Read/Write This register is automatically loaded when a Table Indirect Select or Reselect SCRIPTS instruction is executed. R SCF[2:0] 4-32 Registers Wide SCSI Receive When read, this bit returns the ...
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... Response ID Zero (RESPID0) One (RESPID1) automatically reconfigure itself to the initiator mode as a result of being reselected. SRE Enable Response to Selection When this bit is set, the LSI53C1010R SCSI function is able to respond to bus-initiated selection at the chip ID in the Response ID Zero (RESPID0) SCSI Registers SCF1 ...
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... Reserved Encoded Chip SCSI ID These bits are used to store the LSI53C1010R SCSI function encoded SCSI ID. This is the ID which the chip asserts when arbitrating for the SCSI bus. The IDs that the LSI53C1010R SCSI function responds to when selected or reselected are confi ...
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Ultra160 transfers is counted as the maximum number of data transfers allowed to be outstanding, not the maximum REQ pulses allowed to be outstanding. During ST Data- Data-Out transfers the maximum supported offset is 31 (MO[5:0] = ...
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Register: 0x06 SCSI Destination ID (SDID) Read/Write ENC Register: 0x07 General Purpose (GPREG) Read/Write write to this register will cause the data written to be output to the appropriate GPIO pin ...
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... SCSI First Byte Received This register contains the first byte received in any asynchronous information transfer phase. For example, when a LSI53C1010R SCSI function is operating in the initiator mode, this register contains the first byte received in the Message-In, Status, and Data-In phases. When a Block Move instruction is executed for a particular phase, the fi ...
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... It is controlled by the SCRIPTS processor when executing SCSI SCRIPTS. transferring data using programmed I/O. Some bits are set or cleared when executing SCSI SCRIPTS. Do not write to the register once the LSI53C1010R SCSI function starts executing normal SCSI SCRIPTS. REQ ACK BSY SEL ...
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... ENID Encoded Destination SCSI ID Reading the SSID register immediately after the LSI53C1010R SCSI function is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specifi ...
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... Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C1010R SCSI functions stack interrupts). The DIP bit in the also cleared possible to mask DMA interrupt conditions individually ...
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... Master Parity Error Enable bit (bit 3 of (CTEST4)). BF Bus Fault This bit is set when a PCI bus fault condition is detected. A PCI bus fault can only occur when the LSI53C1010R SCSI function is bus master, and is defined as a cycle that ends with a Bad Address or Target Abort Condition. ABRT Aborted This bit is set when an abort condition occurs ...
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... Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) LSI53C1010R SCSI function is in target mode. During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set. ...
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... SCSI bus, and lost arbitration due to another SCSI device asserting the SSEL/ signal. WOA Won Arbitration When set, WOA indicates that the LSI53C1010R SCSI function has detected a Bus Free condition, arbitrated for SCSI Registers 4 3 ...
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RST SDP0 Register: 0x0E SCSI Status One (SSTAT1) Read Only SDP0L MSG 4-44 Registers the SCSI bus and won arbitration. The arbitration mode selected in the SCSI Control Zero (SCNTL0) must be full arbitration and selection to ...
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C_D SCSI C_D/ Signal This SCSI phase status bit is latched on the asserting edge of SREQ/ when operating in either the initiator or target mode. This bit is set when the corresponding signal is active. This bit is useful ...
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... SCSI Control One detect the case in which a target device disconnects, and then a SCSI device selects or reselects the LSI53C1010R SCSI function. If the Connected bit and the LDSC bit are asserted, a disconnect is indicated. This bit is set when the Connected bit in SCNTL1 is off. This bit is cleared when a Block Move instruction is executed while the Connected bit in SCNTL1 is set ...
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... ABRT Abort Operation Setting this bit aborts the current operation under execution by the LSI53C1010R SCSI function. If this bit is set and an interrupt is received, clear this bit before reading the DMA Status (DSTAT) further aborted interrupts from being generated. The sequence to abort any operation is: 1 ...
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... Semaphore The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C1010R SCSI function is executing a SCRIPTS operation. This bit enables the SCSI function to notify an external processor of a predefined condition while SCRIPTS are running. The external processor may also notify the LSI53C1010R SCSI function of a predefi ...
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... After it has been set, this bit must be written to one to clear it. SIP SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C1010R SCSI function. The following conditions cause a SCSI interrupt to occur: A phase mismatch (initiator mode) or SATN/ becomes ...
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... SRUN SI 4-50 Registers DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C1010R SCSI function. The following conditions cause a DMA interrupt to occur: A PCI parity error is detected A bus fault is detected An abort condition is detected A SCRIPTS instruction is executed in the single-step ...
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INTA/ (or INTB/) pin. If the INTA/ (or INTB/) is already asserted and this bit is set, INT remains asserted until the interrupt is serviced. At this point the interrupt line is blocked for future interrupts until ...
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Register: 0x18 Chip Test Zero (CTEST0) Read/Write 7 1 FMT Register: 0x19 Chip Test One (CTEST1) Read Only 7 0 FFL 4-52 Registers FMT Byte Empty in DMA FIFO These bits identify the lower bytes in ...
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Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write SIGP CIO Reserved SIGP Signal Process This bit is a copy of the SIGP bit in the Zero (ISTAT0) signal a ...
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... When this bit is set, data residing in the DMA FIFO is transferred to memory, starting at the address in the Next Address (DNAD) register. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C1010R SCSI function. Polling of FIFO flags is allowed during flush operations. and Base RAM). This is ...
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... Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C1010R SCSI function is executing SCRIPTS. During any Memory-to-Memory Moves operation, the contents of this register are preserved. The power-up value of this register is indeterminate. ...
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... LSI53C1010R SCSI function is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C1010R SCSI function does not interrupt if a master parity error occurs. This bit is cleared at power-up. ...
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FBL3 FBL2 These bits steer the contents of the (CTEST6) register to the appropriate byte lane of the 64-bit DMA FIFO. If the FBL3 bit is set, then ...
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BBCK R BL2 R Register: 0x23 Chip Test Six (CTEST6) Read/Write 4-58 Registers Clock Byte Counter Setting this bit decrements the byte count contained in the 24-bit DMA Byte Counter (DBC) decremented based on the DBC contents ...
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... Counter (DBC) register is 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DBC register, an illegal instruction interrupt occurs if the LSI53C1010R SCSI function is not in the target mode, Command phase. The DMA Byte Counter (DBC) hold the least significant 24-bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during Table Indirect I/O SCRIPTS ...
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... DNAD 4-60 Registers DCMD DMA Command This 8-bit register determines the instruction for the LSI53C1010R SCSI function to execute. This register has a different format for each instruction. For a complete description see Chapter 5, “SCSI SCRIPTS Instruction Set.” DNAD ...
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Registers: 0x2C–0x2F DMA SCRIPTS Pointer (DSP) Read/Write DSP Registers: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS) Read/Write DSPS SCSI ...
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... This value is also independent of the width (64-bit or 32-bit) of the data transfer on the PCI bus. The LSI53C1010R SCSI function asserts the Bus Request (PCIREQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data ...
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... I/O space; if cleared, the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when a LSI53C1010R SCSI function is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) determine the configuration status of the LSI53C1010R SCSI function. ...
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... BOF MAN 4-64 Registers This function is useful for memory-to-register operations using the Memory Move instruction when a LSI53C1010R SCSI function is I/O mapped. Bits 4 and 5 of the Chip Test Two (CTEST2) determine the configuration status of the LSI53C1010R SCSI function. Enable Read Line This bit enables a PCI Read Line command. If this bit is set and the chip is about to execute a read cycle (other than an opcode fetch), the command is 0b1110 ...
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Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE This register contains the interrupt mask bits corresponding to the interrupting conditions described in the interrupt is masked by clearing the appropriate mask bit. ...
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... The prefetch unit, when enabled, fetches 8 Dwords of instructions and instruction operands in bursts Dwords. Prefetching instructions allows the LSI53C1010R SCSI function to make more efficient use of the system PCI bus, thus improving overall system performance. A flush occurs whenever the PFF bit is set, ...
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... Setting this bit causes the LSI53C1010R SCSI function to stop after executing each SCRIPTS instruction and to generate a single step interrupt. When this bit is cleared the LSI53C1010R SCSI function does not stop after each instruction. It continues fetching and executing instructions until an interrupt condition occurs. For normal SCSI SCRIPTS operation, keep this bit cleared ...
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... Start DMA Operation The LSI53C1010R SCSI function fetches a SCSI SCRIPTS instruction from the address contained in the DMA SCRIPTS Pointer (DSP) set. This bit is required if the LSI53C1010R SCSI function is in one of the following modes: Manual start mode – Bit 0 in the (DMODE) register is set Single-step mode – ...
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Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER Register: 0x40 SCSI Interrupt Enable Zero (SIEN0) Read/Write 7 M/A 0 This register contains the interrupt mask bits corresponding to ...
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... Enable Response to Selection bit in the SCSI Chip ID (SCID) register. Reselected When set, this bit indicates the LSI53C1010R SCSI function is reselected by a SCSI target device. For this to occur, set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register. ...
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... Shadowed SGE Register (ShSGE) bit, in the Two (CCNTL2) UDC Unexpected Disconnect This condition only occurs in the initiator mode. It happens when the target, which the LSI53C1010R SCSI function is connected to, unexpectedly disconnects from the SCSI bus. See the SCSI Disconnect Unexpected bit in the SCSI Control Two (SCNTL2) information on expected versus unexpected disconnects ...
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... Registers Reserved SCSI Bus Mode Change Setting this bit allows the LSI53C1010R to generate an interrupt when the DIFFSENS pin detects a change in voltage level that indicates the SCSI bus has changed between SE, LVD, or HVD modes. For example, when this bit is cleared and the SCSI bus changes modes, IRQ/ does not assert and the SIP bit in the Interrupt Status Zero (ISTAT0) register is not set ...
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... Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending; the LSI53C1010R SCSI functions stack interrupts. SCSI interrupt conditions are individually masked through the SCSI Interrupt Enable Zero (SIEN0) ...
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... SEL RSL SGE 4-74 Registers Selected This bit is set when the LSI53C1010R SCSI function is selected by another SCSI device. For the LSI53C1010R SCSI function to respond to selection attempts, the Enable Response to Selection bit must be set in the Chip ID (SCID) register. The (RESPID0) and Response ID One (RESPID1) must hold the chip’ ...
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... Shadowed SGE Register (ShSGE) bit, in the Two (CCNTL2) UDC Unexpected Disconnect This bit is set when the LSI53C1010R SCSI function is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C1010R SCSI function operates in the initiator mode ...
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... SE, LVD, or HVD modes. Reserved Selection or Reselection Time-Out This bit is set when the SCSI device which the LSI53C1010R SCSI function is attempting to select or reselect does not respond within the programmed time-out period. See the description of the Zero (STIME0) register, bits [3:0], for more information on the time-out timer ...
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See the description of the Zero (STIME0) the handshake-to-handshake timer. Register: 0x44 Reserved This register is reserved. Register: 0x45 SCSI Wide Residue (SWIDE) Read/Write SWIDE SCSI Wide Residue After a ...
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Register: 0x47 General Purpose Pin Control (GPCNTL) Read/Write This register is used to determine if the pins controlled by the Purpose (GPREG) correspond to bits [4:0] in the GPREG register. When the bits are enabled as inputs, ...
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GPIO[1:0] GPIO Enable These bits are set at power-up causing the GPIO1 and GPIO0 pins to become inputs. Clearing these bits cause GPIO[1:0] to become outputs. Register: 0x48 SCSI Timer Zero (STIME0) Read/Write 7 HTH[3: HTH[3:0] Handshake-to-Handshake ...
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SEL[3:0] Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA GENSF 4-80 Registers HTH [3:0], SEL [3:0] 1011 1100 1101 1110 1111 Selection Time-Out These bits select the SCSI selection/reselection time-out period. When this timing (plus the ...
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HTH [3:0], SEL [3:0], GEN [3:0] HTHSF Handshake-to-Handshake Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16. Refer to the description for details. GEN[3:0] General Purpose Timer Period These bits select the period ...
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Register: 0x4A Response ID Zero (RESPID0) Read/Write 7 x RESPID0 Register: 0x4B Response ID One (RESPID1) Read/Write 7 x RESPID1 4-82 Registers RESPID0 Response ID Zero Response ID Zero (RESPID0) (RESPID1) contain the selection or reselection ...
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... ID One (RESPID1) IDs on the bus. SLT Selection Response Logic Test This bit is set when the LSI53C1010R SCSI function is ready to be selected or reselected. This does not take into account the bus settle delay of 400 ns. This bit is used for functional test and fault purposes. ...
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... SCSI operations. When this bit is set and if the LSI53C1010R is functioning as an initiator, the device is waiting for the target to request data transfers. When this bit is set and if the LSI53C1010R is functioning as a target, then the initiator has sent the offset number of acknowledges. SCSI Synchronous Offset Maximum This bit indicates that the current synchronous SREQ/, SACK/ offset is the maximum specifi ...
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... IRM[1:0] Interrupt Routing Mode The LSI53C1010R supports four different interrupt routing modes. These modes are described in the following table. Each SCSI core within the chip can be configured independently. Mode 0, the default mode, is compatible with RAID upgrade products. ...
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... Setting this bit places all the open-drain 48 mA SCSI drivers into a high impedance state. Reserved SCSI Low Level Mode Setting this bit places the LSI53C1010R SCSI function in the low level mode. In this mode, no DMA operations occur and no SCRIPTS execute. Arbitration and selection may be performed by setting the start sequence bit as ...