ST72C334J2 SGS-Thomson-Microelectronics, ST72C334J2 Datasheet
ST72C334J2
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ST72C334J2 Summary of contents
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MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES Memories – 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) – 256 bytes EEPROM Data memory (with ...
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PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 INTRODUCTION . . . . . . ...
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INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72334J/N, ST72314J/N, ST72124J 1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334 8 or 16K FLASH/ROM Programming and Read-out protection New ADC with a better accuracy and conversion time New configurable Clock, Reset and Supply system New ...
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INTRODUCTION The ST72334J/N, ST72314J/N and ST72124J de- vices are members of the ST7 microcontroller fam- ily. They can be grouped as follows: – ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and SCI interface capabilities. ...
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ST72334J/N, ST72314J/N, ST72124J 3 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (HS) PE4 1 (HS) PE5 2 (HS) PE6 3 (HS) PE7 4 ...
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PIN DESCRIPTION (Cont’d) Figure 3. 56-Pin SDIP Package Pinout PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 V DDA V ...
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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts PE1 / RDI PB0 PB1 PB2 PB3 PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN0 / ...
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PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to Section 15 ”ELECTRICAL CHARACTERISTICS” on page 105. Legend / Abbreviations for Table 1: Type input output supply Input level Dedicated analog input ...
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ST72334J/N, ST72314J/N, ST72124J Pin n Pin Name SS_3 PF0/MCO I PF1/BEEP I PF2 I PF4/OCMP1_A I ...
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Pin n Pin Name OSC1 DD_3 PE0/TDO I PE1/RDI I Notes the interrupt input ...
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ST72334J/N, ST72314J/N, ST72124J 4 REGISTER & MEMORY MAP As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register locations, 384 ...
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REGISTER & MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PCDR 0005h Port C PCDDR 0006h PCOR 0007h 0008h PBDR 0009h Port B PBDDR 000Ah PBOR ...
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ST72334J/N, ST72314J/N, ST72124J Register Address Block Label 002Ah WATCHDOG WDGCR 002Bh CRSR 002Ch Data-EEPROM EECSR 002Dh 0030h 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh ...
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Register Address Block Label 0058h 006Fh 0070h ADCDR ADC 0071h ADCCSR 0072h to 007Fh Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of ...
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ST72334J/N, ST72314J/N, ST72124J 5 FLASH PROGRAM MEMORY 5.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool byte-by- byte basis. 5.2 MAIN FEATURES Remote In-Situ Programming ...
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DATA EEPROM 6.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 7. EEPROM Block ...
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 8 describes these different memory access ...
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DATA EEPROM (Cont’d) 6.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler. The DATA EEPROM will immediately enter this mode if there is no programming ...
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h Bit 7:3 = Reserved, forced by hardware to 0. Bit Interrupt enable ...
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CENTRAL PROCESSING UNIT 7.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 7.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit ...
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ST72334J/N, ST72314J/N, ST72124J CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the ...
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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 SP2 The Stack Pointer is a 16-bit register which is al- ways pointing to the ...
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ST72334J/N, ST72314J/N, ST72124J 8 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72334J/N, ST72314J/N and ST72124J mi- crocontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing ...
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LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This means ...
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ST72334J/N, ST72314J/N, ST72124J 8.2 RESET SEQUENCE MANAGER (RSM) 8.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure 15: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act ...
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RESET SEQUENCE MANAGER (Cont’d) 8.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the ...
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ST72334J/N, ST72314J/N, ST72124J 8.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block: an external source 4 crystal or ceramic resonator oscillators an external RC oscillator an ...
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CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a clock filter control and an ...
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ST72334J/N, ST72314J/N, ST72124J 8.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION Read/Write Reset Value: 000x 000x (xxh) 7 LVD CSS Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag ...
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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure ...
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ST72334J/N, ST72314J/N, ST72124J INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET EXECU TE INSTRUCTION Table 6. Interrupt Mapping Source N Description Block RESET Reset TRAP Software Interrupt 0 Not used MCC/RTC Main Clock Controller Time Base Interrupt 1 CSS ...
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POWER SAVING MODES 10.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 19): SLOW, WAIT (SLOW WAIT), AC- ...
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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 10.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain ...
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POWER SAVING MODES (Cont’d) 10.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ...
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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 10.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status ...
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I/O PORTS 11.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O ...
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) Figure 26. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION ...
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I/O PORTS (Cont’d) Table 8. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PU PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O PORTS R PU PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN ...
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is ...
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I/O PORTS (Cont’d) 11.4 LOW POWER MODES Mode Description No effect on I/O ports. External interrupts WAIT cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts HALT cause the device to exit from HALT ...
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) 11.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h ...
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I/O PORTS (Cont’d) Table 10. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 1) 0002h PAOR 0004h PCDR 0005h PCDDR MSB 0006h PCOR ...
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ST72334J/N, ST72314J/N, ST72124J 12 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 12.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx ...
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MISCELLANEOUS REGISTERS (Cont’d) 12.3 REGISTERS DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 CP1 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is ...
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ST72334J/N, ST72314J/N, ST72124J MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h BC1 BC0 - - Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits ...
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ON-CHIP PERIPHERALS 13.1 WATCHDOG TIMER (WDG) 13.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST72334J/N, ST72314J/N, ST72124J WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh ...
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WATCHDOG TIMER (Cond’t) Table 13. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah 0 Reset Value ST72334J/N, ST72314J/N, ST72124J ...
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ST72334J/N, ST72314J/N, ST72124J 13.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock timer ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d) MISCELLANEOUS REGISTER 1 (MISCR1) See Section 12 on page 44. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0001 (01h TB1 TB0 Bit 7:4 = ...
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ST72334J/N, ST72314J/N, ST72124J 13.3 16-BIT TIMER 13.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- ...
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TIMER (Cont’d) Figure 31. Timer Block Diagram f CPU 8 high 8-bit buffer EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 (Status Register) SR ICIE OCIE TOIE ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read LS Byte Byte is buffered Other instructions Returns the buffered Read At t0 ...
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TIMER (Cont’d) Figure 32. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 33. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 13.3.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and ...
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TIMER (Cont’d) Figure 35. Input Capture Block Diagram ICAP1 pin EDGE DETECT EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 36. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 13.3.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an ...
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TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the bit is ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 38. Output Compare Timing Diagram, f INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) ...
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TIMER (Cont’d) 13.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 40. One Pulse Mode Timing Example FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 41. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: ...
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TIMER (Cont’d) 13.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 13.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until ...
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TIMER (Cont’d) 13.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT ...
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TIMER (Cont’d) Table 16. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 Reset Value 0 Timer ...
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ST72334J/N, ST72314J/N, ST72124J 13.4 SERIAL PERIPHERAL INTERFACE (SPI) 13.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 43. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS ST72334J/N, ST72314J/N, ST72124J Internal Bus DR SPIF WCOL SPI STATE CONTROL SPIE SPE SPR2 MSTR MASTER CONTROL SERIAL ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4 Functional Description Figure 42 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 45. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit Bit 6 MISO (from master) MSBit Bit 6 MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) Table 18. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPISR SPIF 0023h Reset Value 0 82/148 6 ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 13.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 48. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE ILIE SCI INTERRUPT CONTROL TRANSMIT TER CLOCK f CPU /2 /16 84/148 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 48. It contains 6 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status register (SR) – A ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 50. SCI Baud Rate and Extended Prescaler Block Diagram EXTE NDED PRESCALER TRANSMITTE R RATE CONTROL EXTE NDED TRANS MITTER PRESCALE R REGISTER EXTE NDED RECEIVER PRESCALER REGISTER EXTE NDED PRESCALER RECEIVER ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows CPU (32 (32 PR ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR NF Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAK E - Bit Receive data bit 8. This bit is used to store the 9th bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 DR2 The Data register ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ERPR ...
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A/D CONVERTER (ADC) 13.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) 13.6.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If ...
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A/D CONVERTER (ADC) (Cont’d) 13.6.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 CH2 Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by ...
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 20. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Reset Value 0 98/148 ...
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INSTRUCTION SET 14.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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ST72334J/N, ST72314J/N, ST72124J ST7 ADDRESSING MODES (Cont’d) 14.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction Function NOP No operation TRAP ...
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ST7 ADDRESSING MODES (Cont’d) 14.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST72334J/N, ST72314J/N, ST72124J 14.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory tst ( ...
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ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Unsigned <= LD Load dst <= src MUL Multiply X NEG Negate (2’s compl) neg $10 NOP No Operation OR ...
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ELECTRICAL CHARACTERISTICS 15.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 15.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ST72334J/N, ST72314J/N, ST72124J 15.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 15.2.1 ...
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OPERATING CONDITIONS 15.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 55. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALI TY NOT GUARANTEED ...
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ST72334J/N, ST72314J/N, ST72124J OPERATING CONDITIONS (Cont’d) 15.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter V Reset release threshold (V IT Reset generation threshold (V IT- V LVD voltage threshold ...
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FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 60. High LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 3 Figure 61. Medium LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN ...
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ST72334J/N, ST72314J/N, ST72124J 15.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter I ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 15.4.2 WAIT and SLOW WAIT Modes Symbol Parameter 3) Supply current in WAIT mode (see Figure 65) Supply current in SLOW WAIT mode (see Figure 66 Supply current in WAIT mode (see Figure ...
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ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d) 15.4.3 HALT and ACTIVE-HALT Modes Symbol Parameter Supply current in HALT mode I DD Supply current in ACTIVE-HALT mode 15.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 15.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) 2) Interrupt reaction time t v(IT v(IT) c(INST) 15.5.2 External Clock Source Symbol ...
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ST72334J/N, ST72314J/N, ST72124J CLOCK AND TIMING CHARACTERISTICS (Cont’d) 15.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 15.5.4 Typical Ceramic Resonators Symbol Parameter t Ceramic resonator startup time SU(osc) Note the typical oscillator start-up time measured between V SU(OSC) quick V ramp-up from (<50 s). DD Figure ...
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ST72334J/N, ST72314J/N, ST72124J CLOCK AND TIMING CHARACTERISTICS (Cont’d) Table 23. Typical Ceramic Resonators f Option Byte OSC Resonator Part Number Config. (MHz) CSB1000JA 1 CSBF1000JA LP CSTS0200MGA06 2 CSTCC2.00MGA0H6 CSTS0200MGA06 2 CSTCC2.00MGA0H6 MP CSTS0400MGA06 4 CSTCC4.00MGA0H6 CSTS0400MGA06 4 CSTCC4.00MGA0H6 MS ...
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CLOCK CHARACTERISTICS (Cont’d) 15.5.5 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal Symbol Parameter Internal RC oscillator frequency f OSC External RC oscillator frequency Internal RC Oscillator Start-up ...
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ST72334J/N, ST72314J/N, ST72124J CLOCK CHARACTERISTICS (Cont’d) 15.5.6 Clock Security System (CSS) Symbol Parameter 1) f Safe Oscillator Frequency SFOSC 2) f Glitch Filtered Frequency GFOSC Figure 73. Typical Safe Oscillator Frequencies fosc [kHz] -40 C +85 C 400 +25 C ...
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MEMORY CHARACTERISTICS 15.6.1 RAM and Hardware Registers Symbol Parameter 1) V Data retention mode RM 15.6.2 EEPROM Data Memory Symbol Parameter t Programming time for 1~16 bytes prog 5) t Data retention ret 5) N Write erase cycles RW ...
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ST72334J/N, ST72314J/N, ST72124J 15.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 15.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the ...
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EMC CHARACTERISTICS (Cont’d) 15.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer ...
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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) 15.7.2.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to ...
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EMC CHARACTERISTICS (Cont’d) 15.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electro- Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. The stress generally affects the circuit el- ements ...
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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode ...
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I/O PORT PIN CHARACTERISTICS 15.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter 2) V Input low level voltage Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input leakage ...
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ST72334J/N, ST72314J/N, ST72124J I/O PORT PIN CHARACTERISTICS (Cont’d) 15.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 87. Typical V vs. V (standard I/Os Vol [V] at Iio=2mA Ta=-40 C 0.5 Ta=25 C 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 Vdd [V] Figure 88. Typical V ...
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ST72334J/N, ST72314J/N, ST72124J 15.9 CONTROL PIN CHARACTERISTICS 15.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter 2) V Input low level voltage Input high level voltage IH V Schmitt trigger voltage hysteresis hys ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 91. Typical I vs. V with Ion [ A] Ta=-40 C Ta=85 C 200 Ta=25 C Ta=125 C 150 100 50 0 3.2 3.5 4 4.5 Vdd [V] Figure 93. Typical V ...
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ST72334J/N, ST72314J/N, ST72124J CONTROL PIN CHARACTERISTICS (Cont’d) 15.9.2 ISPSEL Pin Subject to general operating conditions for V Symbol Parameter 1) V Input low level voltage Input high level voltage IH I Input leakage current L Figure 94. ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 15.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 15.10.2 16-Bit Timer Symbol Parameter t Input capture pulse time ...
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ST72334J/N, ST72314J/N, ST72124J 15.11 COMMUNICATION INTERFACE CHARACTERISTICS 15.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 96. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL w(SCKH) a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI MSB IN INPUT Figure 97. ...
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ST72334J/N, ST72314J/N, ST72124J COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) 15.11.2 SCI - Serial Communications Interface Subject to general operating condition for V , and T unless otherwise specified Refer to I/O port characteristics for more details on the input/output alternate ...
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ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC 2) V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ...
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ST72334J/N, ST72314J/N, ST72124J 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity ...
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PACKAGE CHARACTERISTICS 16.1 PACKAGE MECHANICAL DATA Figure 100. 64-Pin Thin Quad Flat Package L1 Figure 101. 56-Pin Shrink Plastic Dual In-Line Package, 600-mil Width ST72334J/N, ST72314J/N, ST72124J Dim Min A A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 ...
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ST72334J/N, ST72314J/N, ST72124J PACKAGE MECHANICAL DATA (Cont’d) Figure 102. 44-Pin Thin Quad Flat Package L1 Figure 103. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width 138/148 Dim Min A A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 ...
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THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the port power dissipation determined ...
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ST72334J/N, ST72314J/N, ST72124J 16.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 104 and Figure 105. Figure 104. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 80 C Temp. ...
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PACKAGE/SOCKET FOOTPRINT PROPOSAL 16.4.1 User-supplied TQFP64 Adaptor / Socket To solder the TQFP64 device directly on the appli- cation board solder a socket for connecting the emulator probe, the application board should provide the footprint described in ...
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ST72334J/N, ST72314J/N, ST72124J PACKAGE/SOCKET FOOTPRINT PROPOSAL (Cont’d) 16.4.2 User-supplied TQFP44 Adaptor / Socket To solder the TQFP44 device directly on the appli- cation board solder a socket for connecting the emulator probe, the application board should provide the ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory 2 coded versions (ROM). E PROM data memory and FLASH devices are shipped to customers with a ...
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... T = Plastic TQFP ST72334J2, ST72334J4, ST72334N2, ST72334N4, ST72314J2, ST72314J4, ST72314N2, ST72314N4, ST72124J2 Code name (defined by STMicroelectronics standard industrial - automotive -40 to +105 automotive -40 to +125 Plastic DIP T = Plastic TQFP ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4, ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4, ST72C124J2 ...
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ST72334/314/124 ROM MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72334J/N, ST72314J/N, ST72124J 17.2 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tain from the ...
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SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Figure 56 on page 107 updated. V Min. value changed from 3.0 to 3.2V in Section 15.3.1 on page 107. ...
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ST72334J/N, ST72314J/N, ST72124J Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may ...