STLC60134S SGS-Thomson-Microelectronics, STLC60134S Datasheet
STLC60134S
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STLC60134S Summary of contents
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... ACCURATE CONTINUOUS-TIME CHANNEL FILTERING 3rd & 4th ORDER TUNABLE CONTINUOUS TIME LP FILTERS 0.5 WATT AT 3.3V 0.5 m HCMOS5 LA TECHNOLOGY 64 PIN TQFP PACKAGE DESCRIPTION STLC60134S is the Analog Front End of the STMicroelectronics Tosca ADSL chipset and when coupled with STLC60135 (DTM modem) al- Figure 1. Block Diagram G=-15...0dB step=1dB TXP ...
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... See chapter ’VCXO’ for the external circuit re- lated to the VCXO . The Digital Interface part The digital part of the STLC60134S can be di- vided in 3 sections: The data interface converts the multiplexed data from/to the DMT signal processor into valid representation for the TX DAC and RX ADC ...
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... The reference line impedance for all power calcu- lations is 100 . PACKAGE The STLC60134S is packaged in a 64-pin TQFP package (body size 10x10mm, pitch 0.5mm). ATU - 15.8 Vpdif 3.95 Vpdif 3 ...
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... STLC60134S Table 3. Pin Functions. N. Name ANALOG INTERFACE 24 VRAP positive voltage reference ADC 25 VREF ground reference ADC 26 VRAN negative voltage reference ADC 31 TXP pre driver output 32 TXN pre driver output 38 AGND virtual analog ground (AVDD/2 = 1.65V) 44 VCOC VCODAC time constant capacitor 45 GC0 ...
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... On the RX path filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to re- duce crosstalk between STLC60134S signals and POTS speech and signalling. STLC60134S AVDD AVSS ...
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... STLC60134S Figure 4. ATU-C END Block Diagram. POTS LINE LP Zo=100 POTS FILTER 2:1 HP POTS FILTER RXT1 RXT2 R R RXP(0:1) 12.5 12.5 LPF GRX RXN(0: GTX LINE DRIVER HPF ATU-R END: BLOCK DIAGRAM The ATU-R side block diagram is equal to the ATU-C side block diagram with the following dif- ...
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... The combination of the external filter (an LC lad- der filter typically) with the integrated lowpass fil- ter must provide: - echo reduction to improve dynamic range -1/2 seen - DMT sidelobe and out of band (anti-aliasing) attenuation. - Anti alias filter (60dB rejection @ image freq.) STLC60134S Value/Unit 1.6V < V <1. Value/Unit -1/2 20nVHz ...
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... STLC60134S ATU-R RX Filters The integrated filter have the following characteristics: Table 6. Integrated HC Filter Characteristics Description Input referred noise Max. input level Max. output level Type Frequency band Frequency tuning Max. in-band ripple Matlab Model Default cut off frequency @ -3dB Actual cut off @ -3dB HC Freq ...
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... Power Supply Rejection The noise on the power supplies for the RX path must be lower than the following: <50mVrms in band white noise for any AVDD. In this case, PSR (power supply rejection) of STLC60134S RX path is lower than -43dB. TX PATH Transmitter Spectral Response The two figures below show the ANSI spectral response mask for ATU-C and ATU-R transmitters Figure 8 ...
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... STLC60134S Table 12. AGC of TX Path (from filter output to TXP and TXN). Output noise Input level (nominal) Output level nominal, full-scale Maximum Output Load AGC range: AGC step: Gain and step accuracy Minimum code (0000) stands for AGC = -15dB and maximum (1111 - MSB left) for AGC = 0dB (See Tx setting, Table22) ...
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... D98TL363 12bits 11bits <1LSB (out of 12bits) 1 Vpdif 5% 8.832MHz (or 4.416MHz in compatible mode) <3 s <1 s 500kHz 400kHz 59.5dB @ 300kHz 48.0dB @ 600kHz STLC60134S Value/Unit < 34.5kHz < f < 138kHz < 34.5kHz < f < 138kHz KHz Value/Unit 700kHz 600kHz 48.0dB @ 500kHz 42.5dB @ 800kHz 11/22 ...
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... AVDD. < 15mVrms in-band white noise for Pre-driver AVDD. VCXO A voltage controlled crystal oscillator driver is integrated in STLC60134S. The nominal frequency is 35.328MHz. The quartz crystal is connected between the pins XTALI and XTALO. The principle of the VCXO control is shown in figure 11. ...
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... VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt. Min. Nominal -15ppm 35.328MHz 50ppm 100 A 100 AVDD C S VCOCX AVDD/22 AVDD/2 IVCO VCXOUT Clk35 XTALO C P XTALI STLC60134S Max. Note +15ppm Rref = 16.5k AVDD = 3.3V 1mA AVDD = 3.3V AVDD AGND -15V D98TL364mod ( 13/22 ...
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... DIGITAL INTERFACE Control Interface The digital setting codes for the STLC60134S configuration are sent over a serial line (CTRLIN) using the word clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (’0’), the three LSBs be- ing used to identify the data contained in the 12 remaining bits ...
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... XTAL in powerdown RESERVED RESERVED RESERVED STLC60134S AFE SETTINGS (init) (init) (*) (*) (*) (init) (*) (*) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) RESERVED 15/22 ...
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... STLC60134S Control Interface Timing The word clock (CLWD) is used to sample at negative going edge the control information. The start bit b15 is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the data. Figure 12. Control Interface. CLWD CTRLIN START BIT Data set-up and hold time versus falling edge CLWD must be greater than 10nsec ...
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... CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces. Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the falling edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital proces- sor. Data, CLWD setup and hold times are 5ns with reference to the falling edge of CLKM/CLKNIB. ...
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... Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital processor. Data,CLWD setup and hold times are 5ns with reference to thefalling edgeof CLKM/CLKNIB. (not floating). ...
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... AVDD Supply Voltage, related to substrate DVDD DVDD Supply Voltage, related to substrate V /V Voltage at any input and output pin in out P Power Dissipation d T Ambient Temperature amb T Junction Temperature j Parameter Parameter Parameter STLC60134S Min Max Unit - 0 -0 -40 125 C 300 C 100 mA 165 ...
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... STLC60134S STATIC CHARACTERISTICS Table 30. Digital Inputs Schmitt-trigger inputs: TXi, CTRLIN, PDOWN, LTNT, RESETN, TEST Symbol Parameter V Low Level Input Voltage IL V High Level Input Voltage IH V Hysteresis H C Input Capacitance imp Table 31. Digital Outputs Hard Driven Outputs: RXi Symbol Parameter V Low Level Output Voltage ...
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... B 0.18 0.23 0.28 0.007 0.009 C 0.12 0.16 0.20 0.0047 0.0063 0.0079 D 12.00 0.472 D1 10.00 0.394 D3 7.50 0.295 e 0.50 0.0197 E 12.00 0.472 E1 10.00 0.394 E3 7.50 0.295 L 0.40 0.60 0.75 0.0157 0.0236 0.0295 L1 1.00 0.0393 K (min.), 7 (max OUTLINE AND MECHANICAL DATA MAX. 0.063 0.006 0.057 0.011 TQFP64 TQFP64 STLC60134S 0.10mm Seating Plane C 21/22 ...
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... STLC60134S Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...