STA015 SGS-Thomson-Microelectronics, STA015 Datasheet
STA015
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STA015 Summary of contents
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... Input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Out- put Interface. This interface is software program- mable to adapt the STA015 digital output to the most common DACs architectures used on the market. The functional STA015 chip partitioning is de- scribed in Fig ...
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... STA015-STA015B-STA015T Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package TQFP44 34 SDI SERIAL 36 SCKR INPUT INTERFACE 38 BIT_EN 27 BUFFER DATA-REQ 256 SCK_ADC ADC 26 CRCK_ADC INPUT INTERFACE 24 SDI_ADC 25 15 RESET XTI Figure 1b. BLOCK DIAGRAM for SO28 package SO28 5 SDI SERIAL 6 SCKR INPUT INTERFACE ...
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... C8 = VDD_4 F2 = SCKT D7 = TESTEN H1 = LRCKT A7 = SDI_ADC H3 = OCLK B6 = RESET F3 = VSS_2 A5 = LRCK_ADC E4 = VDD_2 C5 = OUT_CLK/DATA_REQ G4 = VSS_3 B5 = VDD_1 G5 = VDD_3 B4 = VSS_1 F5 = PVDD A4 = SDA G6 = PVSS B3 = SCL LFBGA64 STA015-STA015B-STA015T C2 = GPIO_STROBE C3 = IODATA [ IODATA [ IODATA [ IODATA [ GPSO_REQ F8 = IODATA [ IODATA [ IODATA [ IODATA [ GPSO_SCKR A2 = GPSO_DATA 3/44 ...
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... STA015-STA015B-STA015T 1. OVERVIEW 1.1 - MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also per- forms ANCILLARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order to implement specific functions ...
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... F1 IODATA[ GPIO_STROBE 4 G3 GPSO_REQ 28 C6 GPSO_SCKR 33 A2 GPSO_DATA Note: In functional mode TESTEN must be connected to VDD. STA015-STA015B-STA015T Type Function Supply Voltage Ground 2 I Serial Data + CMOS Input Pad Buffer Acknowledge CMOS 4mA Output Drive Serial Clock CMOS Input Pad Buffer ...
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... STA015-STA015B-STA015T 1. ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol Parameter V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic Protection esd Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin ...
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... OUTPUT FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA015 input clock is derivated from an ex- ternal source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 MHz. Symbol Parameter V Low Level Input Voltage IL V High Level Input Voltage ...
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... Data can be output either with the most significant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the several STA015 PCM Output Formats. The sample rates set decoded by STA015 is de- scribed in Table 1. 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles M ...
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... In this mode the fractional part of the PLL is dis- abled and the audio clocks are generated at nominal rates. Fig. 7 describes the default DATA_REQ signal behaviour. Programming STA015 it is possible to invert the polarity of the DATA_REQ line (register REQ_POL). Figure 7. SOURCE STOPS TRANSMITTING DATA SOURCE STOPS TRANSMITTING DATA ...
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... The operation is done by STA015 em- beddedsoftware and it is transparentto the user. The STA015 PLL can drive directly most of the com- mercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. ...
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... SCK_ADC SDI SCKR SERIAL RECEIVER DATA_REQ STA015-STA015B-STA015T GPSO_SCKR GPSO_DATA STA015 MCU GPSO_REQ D00AU1145 ADPCM to provide an interrupt; the use of the other bits is still to be defined. The related con- figuration register is GPIO_CONF. See the follow- ing summary for related pin usage: Name Description ...
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... The device that controls the data transfer is known as the master and the others as the slave. The master always starts the transfer and provides the serial clock for synchro- nisation. The STA015 is always a slave device in all its communications. 12/44 Figure 12. Input from BITSTREAM, Output from ...
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... SCL line is low. 3.2 - DEVICE ADDRESSING To start communication between the master and the STA015, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode ...
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... This mode can be initiated with either a current address read or a random address read. How- ever in this case the master does acknowledge the data byte output and the STA015 continues to output the next byte in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte, but ...
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... ADC_ WLEN $C1 193 ADC_ WPOS $C2 194 ADPCM_SKIP_FRAME Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use. STA015-STA015B-STA015T DESCRIPTION RESET 0xFF 0x5B 0x0F R/W R/W (8) 0x00 R/W (2) 0x00 R/W (1) ...
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... Address: 0x07 (07 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The M and N registers are used to configure the STA015 PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA015, by DSP soft- ware. LSB SYS2O PPLD XTI2DS ...
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... don’t care normal operation reset LSB When this register is written, a soft reset occours The STA015 core command register and the in (1) terrupt register are cleared. The decoder goes (2) to idle mode. PLAY Address: 0x13 (19) ...
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... X = don’t care normal operation write into I C/Ancillary Data The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Registers: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register, setting non-zero value ...
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... H20 H19 H18 x = don’t care HEAD_M[15:8] MSB H15 H14 H13 H12 H1‘1 H10 STA015-STA015B-STA015T HEAD_L[7:0] MSB Address: 0x43, 0x44, 0x45 (67, 68, 69) LSB b1 b0 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy ...
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... STA015-STA015B-STA015T Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID. bitrate index ’0000’ free ’0001’ 32 ’0010’ 40 ’0011’ 48 ’0100’ 56 ’0101’ 64 ’0110’ 80 ’0111’ 96 ’1000’ 112 ’1001’ 128 ’1010’ 160 ’1011’ 192 ’ ...
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... DRA register is used to attenuate the level of audio output at the Right Channel using the but- terfly shown in Fig. 11. When the register is set to STA015-STA015B-STA015T 255 (0xFF), the achieved. A decimal unit correspond to an attenuation step of 1 dB. DLA Output Left Channel X + ...
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... STA015-STA015B-STA015T DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB DRB7 DRB6 DRB5 DRB4 DRB register is used to re-direct the Right Chan- nel on the Left mix both the Channels. ...
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... PF15 PF14 PF13 PF12 PF11 PF10 PF9 The registers are considered logically concate- nated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H regis- ters) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W STA015-STA015B-STA015T Software Reset: 0x00 Hardware Reset: 0x00 MSB ...
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... STA015-STA015B-STA015T The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCM_DIV = (O_FAC/64 bit mode ...
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... INV_LRCLK=1 ’01’: 18 bit mode (32 slots transmitted) ’10’: 20 bit mode (32 slots transmitted) ’11’: 24 bit mode (32 slots transmitted) The PCM samples precision in STA015 can 18-20-24 bits. When STA015 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period is 32 (64). ...
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... The register contains the values for PLL X divider (see Fig. 7). The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface con- figuration. The VCO output frequency is divided by (X+1). ...
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... LSB Setting this register to 1, STA015 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been in- itialized. TREBLE_FREQUENCY_LOW Address: 0x77 (119) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 ...
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... TE7 TE6 TE5 Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Treble Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhan cement range is [-18dB, +18dB]. ...
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... STA015-STA015B-STA015T This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. LSB The allowed Attenuation/Enhan cement range [-18dB, +18dB]. ...
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... STA015-STA015B-STA015T TONE_ATTEN Address: 0x7D (125) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB TA7 TA6 TA5 TA4 TA3 TA2 In the digital output audio, the full signal is achieved with attenuation. For this rea- MSB ...
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... MPEG frame, the ANCCOUNT_L and ANC- COUNT_H registers (0x41 and 0x42) have to be read. The buffer dimension is 5 bytes, written by STA015 core in sequential order. So the whole set of ancillary data may be accessed in one shot. The timing information to read the buffer can be obtained by reading the FRAME_CNT registers (0x67 - 0x69) ...
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... STA015-STA015B-STA015T GPSO_CONF Address: 0xBA (186) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB GSP: GPSO Sclk polarity Using this bit the GPSO_SCLK polarity can be controlled. Clearing GSP bit data on GPSO_DATA line will be provided on the rising edge of GPSO_SCLK (sampling on falling edge) ...
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... Using this register the ADPCM interrupt capability can be properly configured. INTL0 - Interrupt Length INTL6 The interrupt length can be programmed, using this bits, from 128 system clock cycles STA015-STA015B-STA015T GPIO_CONF Address: 0xBF (191) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 LSB MSB ...
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... STA015-STA015B-STA015T The STA015 contains 56 consecutive 8-bit regis- ters corresponding to the maximum number of ancillary data that may be contained in MPEG frame. The ANCCOUNT_L and ANCOUNT_H registers contain the number of ancillary data bits available within the current MPEG frame. To perform ancillary data reading a status regis- ...
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... OCLK) b) OCLK in input. OCLK (INPUT) SDO SCKT LRCLK Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns STA015-STA015B-STA015T t sdo t sckt t lrclk D98AU969 Pad-timing versus load Load (pF 100 Cload_XXX is the load the XXX output ...
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... STA015-STA015B-STA015T 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0 BIT_EN SCKR IGNORED SDI 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1 BIT_EN SCKR IGNORED SDI tsdi_setup_min= 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT This is an asynchronous input used in ”broadcast’ mode. ...
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... SCLK_POL set DATA_REQ_ENABLE set REQ_POL set RUN STA015-STA015B-STA015T t reset_low_min PCM OUTPUT INTERFACE THE OVERALL CONFIGURATION SETTING STEPS ARE INCLUDED IN THE STA015 CONFIGURATION FILE AND CAN BE DOWNLOADED PLL IN ONE STEP. CONFIGURATION STM PROVIDES FOR: A SPECIFIC CONFIGURATION { 48, 44.1, 32 FILE FOR EACH 29, 22.05, 16 SUPPORTED 12, 11 ...
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... STA015-STA015B-STA015T Table 5: PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 6: PLL Configuration Sequence For 10MHz Input Clock 384 Oversapling Rathio REGISTER NAME ADDRESS ...
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... Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL STA015-STA015B-STA015T Table 11: PLL Configuration Sequence For 14.7456MHz Input Clock 384 Oversapling Rathio REGISTER VALUE ADDRESS 11 6 reserved 3 11 reserved 6 97 MFSDF ( MFSDF-441 3 101 ...
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... Note:1 STA015 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable. Note 2: ...
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... DIM. MIN. TYP. MAX. MIN. TYP. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 0.020 c1 45 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 L 0.4 1.27 0.016 S 8 (max.) STA015-STA015B-STA015T OUTLINE AND MECHANICAL DATA MAX. 0.104 0.012 0.019 0.013 0.713 0.419 0.299 0.050 SO28 41/44 ...
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... STA015-STA015B-STA015T mm DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.30 0.37 0.45 0.012 C 0.09 0.20 0.004 D 12.00 D1 10.00 D3 8.00 e 0.80 E 12.00 E1 10.00 E3 8.00 L 0.45 0.60 0.75 0.018 L1 1.00 K (min.), 3.5 (typ.), 7 (max 42/44 inch OUTLINE AND TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.014 0.018 0.008 0.472 0.394 0.315 0.031 ...
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... D1 5.600 0.220 e 0.800 0.031 E 8.000 0.315 E1 5.600 0.220 f 1.200 0.047 BALL 1 IDENTIFICATION (64 PLACES) e STA015-STA015B-STA015T OUTLINE AND MECHANICAL DATA MAX. 0.067 0.018 Body 1.7mm LFBGA64 0. LFBGA64M D E 43/44 ...
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... STA015-STA015B-STA015T Information furnished is believed to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...