TS5070 SGS-Thomson-Microelectronics, TS5070 Datasheet

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TS5070

Manufacturer Part Number
TS5070
Description
PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION
Manufacturer
SGS-Thomson-Microelectronics
Datasheet

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DESCRIPTION
The TS5070series are the second generationcom-
bined PCM CODEC and Filter devices optimized
for digital switching applications on subscriber and
trunk line cards.
Using advanced switched capacitor techniques the
TS5070 and TS5071 combine transmit bandpass
and receive lowpass channel filters with a com-
panding PCM encoder and decoder. The devices
are A-law and -law selectable and employ a con-
ventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programma-
ble functions may be controlled via a serial control
port.
December 1997
INCLUDING :
SLICs
WINDING SECONDARY
LSSGR SPECIFICATIONS
TERFACES
COMPLETE CODEC AND FILTER SYSTEM
– TRANSMIT AND RECEIVE PCM CHANNEL
– RECEIVE POWER AMPLIFIER DRIVES
– 4.096 MHz SERIAL PCM DATA (max)
PROGRAMMABLE FUNCTIONS :
– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB
– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB
– HYBRID BALANCE CANCELLATION FIL-
– TIME-SLOT ASSIGNMENT: UP TO 64
– 2 PORT ASSIGNMENT (TS5070)
– 6 INTERFACE LATCHES (TS5070)
– A OR -LAW
– ANALOG LOOPBACK
– DIGITAL LOOPBACK
DIRECT
SIMPLIFIES TRANSFORMER SLIC, SINGLE
STANDARD SERIAL CONTROL INTERFACE
80 mW OPERATING POWER (typ)
1.5mW STANDBY POWER (typ)
MEETS OR EXCEEDS ALL CCITT AND
TTL AND CMOS COMPATIBLE DIGITAL IN-
FILTERS
AND DECODER
300
STEPS
STEPS
TER
SLOTS/FRAME
-LAW OR A-LAW COMPANDING CODER
INTERFACE
TO
SOLID-STATE
PROGRAMMABLE CODEC/FILTER
Channel gains are programmable over a 25.4 dB
range in each direction, and a programmable filter
is included to enable Hybrid Balancing to be ad-
justed to suit a wide range of loop impedance con-
ditions.
Both transformer and active SLIC interface circuits
with real or complex termination impedances can
be balanced by this filter, with cancellation in ex-
cess of 30 dB being readily achievable when meas-
ured across the passbandagainst standardtest ter-
mination networks.
To enable COMBO IIG to interface to the SLIC con-
trol leads, a number of programmable latches are
included ; each may be configured as either an in-
put or an output. The TS5070 provides 6 latches
and the TS5071 5 latches.
COMBO 2
ORDERING NUMBERS: TS5070FN
ORDERING NUMBER:TS5071N
DIP20 (Plastic)
ND
PLCC28
GENERATION
TS5070FNTR
TS5070
TS5071
1/32

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TS5070 Summary of contents

Page 1

... To enable COMBO IIG to interface to the SLIC con- trol leads, a number of programmable latches are included ; each may be configured as either an in- put or an output. The TS5070 provides 6 latches and the TS5071 5 latches. TS5070 TS5071 TS5070FNTR ...

Page 2

... TS5070 - TS5071 TS5070 PIN FUNCTIONALITY (PLCC28) No. Name 1 GND Ground Input (+0V Analog Output Supply Input (-5V Not Connected 5 NC Not Connected 6 IL3 Digital Input or Output defined by LDR register content 7 IL2 Digital Input or Output defined by LDR register content 8 FS ...

Page 3

... GND SS SS Voltage at VFXI V Voltage at Any Digital Input IN Current at VFRO I Current at Any Digital Output O T Storage Temperature Range stg T Lead Temperature Range (soldering, 10 seconds) lead Parameter TS5070 - TS5071 Value Unit 7 V – 0 – 0 0.5 to GND – 0 100 ...

Page 4

... TS5070 - TS5071 PIN CONNECTIONS PLCC28 TS5070FN POWER SUPPLY, CLOCK Pin TS5070 TS5071 Name Type GND BCLK MCLK 4/32 Function Positive Power + Supply Negative – Power Supply Ground All analog and digital signals are referenced to this pin. ...

Page 5

... R as voice frequency signals. Receive Data available on the TS5070 only all devices. These receive data input(s) are inactive except during the assigned receive time–slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK ...

Page 6

... Table 1. Control Data These are separate controls, availables only on the Input TS5070. They can be wired together if required. Control Data Output Chip Select When this pins is low, control information can be written to or read from the COMBO IIG via the CI and CO pins (or CI/O) ...

Page 7

... COMBO IIG via the serial control port consistingof the controlclock CCLK ; the serial data input/ou tput CI/O (or separate input CI, and output CO on the TS5070 only) ; and the Chip Se- lect input CS. All control instructions require 2 bytes,as listed in table 1, with the exceptionof a sin- gle byte power-up/down command ...

Page 8

... TS5070 - TS5071 struction; and bit 0 is not used. To shift control data into COMBO IIG, CCLK must be pulsed high 8 timeswhile CS is low. Data on the CI or CI/O input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted ...

Page 9

... TS5070 - TS5071 O output, forming pin remains ac- R Function * * * * * A-law without even bit inversion MSB LSB ...

Page 10

... TS5070 - TS5071 This mode provides another stage of path verifica- tion by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot For Analog Loopback as well as for Digital Loop- back PCM decoding continues and analog output appears ...

Page 11

... Time-Slot Assignment mode requires that the FS and FS pulses must conformto the delayedtiming R format shown in figure 6. PORT SELECTION On the TS5070 only, an additional capability is available : 2 Transmit serial PCM ports and 2 receive serial PCM ports are provided to enable two-way space switching to be implemented. Port selections for transmit and receive are made within the appropriate time-slot Table 7: Byte 2 of Transmit Gain Instructions ...

Page 12

... TS5070 - TS5071 Table 8: Byte 2 of Receive Gain Instructions. Bit Number Notes: 1. Maximum level into 300 ; 2. Maximum level into 600 ; ...

Page 13

... An Hybrid Balance filter design guide and soft- ware optimization program are available under li- cense from SGS-THOMSON Microelectronics (or- der TS5077-2). TS5070 - TS5071 . If the (1) Function ...

Page 14

... TS5070 - TS5071 APPLICATION INFORMATION Figure 2 shows a typical application of the TS5070 together with a transformer SLIC. The design of the transformer is greatly simplified due to the on-chip hybrid balancecancellation filter. Only one single secondary winding is required (see application note AN.091 - Designing a subscriber line card module using the TS5070/COMBO IIG). ...

Page 15

... Figure 2: Transformer SLIC + COMBO IIG. TS5070 - TS5071 15/32 ...

Page 16

... TS5070 - TS5071 Figure 4: Interface with L3092 + L3000 Silicon SLIC. 16/32 ...

Page 17

... All signals referencedto GND. Typicals specified 3.2mA L = -3.2mA -1mA < < V < < 3.3V < 3.3V) X TS5070 - TS5071 = 25 C. All other limits Min. Typ. Max. Unit 0.7 V 2.0 V 0.4 V 2 -10 100 ...

Page 18

... Period of MCLK High (measured from V WMH t Period of MCLK Low (measured from V WML t Rise Time of MCLK (measured from Fall Time of MCLK (measured from Hold Time, BCLK Low to MCLK High (TS5070 only) HBM t Period Low (Measured from V WFL X R (*) MCLK period 18/32 Min. ...

Page 19

... Hold Time, BCLK Low to DR0/1 Invalid HBD Figure 5: Non Delayed Data Timing (short frame mode) Min High or Low (if BCLK8 low); (if FSx still high); TS5070 - TS5071 Typ. Max. Unit 64 4096 kHz ...

Page 20

... TS5070 - TS5071 Figure 6: Delayed Data Timing (short frame mode) SERIAL CONTROL PORT TIMING Symbol Parameter f Frequency of CCLK CCLK t Period of CCLK High (measured from V WCH t Period of CCLK Low (measured from V WCL t Rise Time of CCLK (measured from Fall Time of CCLK (measured from V ...

Page 21

... Figure 7: Control Port Timing 21/32 TS5070 - TS5071 ...

Page 22

... – =-40 Cto correlation SS A with 100 % electrical testing (- for TS5070-X and TS5071-X). AMPLITUDE RESPONSE Symbol Parameter Absolute levels The nominal 0 dBm 0 levels are : Gain X 25 Gain ...

Page 23

... Note: 0.1dB min/max is available as a selected part Calculate the Deviation from the Programmed Gain Relative to GRA I.e. GRAG = Gactual - Gprog - GRA T 23/32 Parameter Measure =1015.625Hz 5V - TS5070 - TS5071 Min. Typ. Max. Unit -26 dB -1.8 -0.1 dB -0.15 0. -14 ...

Page 24

... TS5070 - TS5071 AMPLITUDE RESPONSE (continued) Symbol GRAT Receive Gain Variation with Temperature Measure Relative to GRA -5V -17dBm < 0dBm0 < 8.1dBm CC SS GRAV Receive Gain Variation with Supply Measured Relative to GRA 5 - 0dBm 0 = 8.1 dBm A GRAF Receive Gain Variation with Frequency Relative to 1015 ...

Page 25

... 2800 – 3000 Hz DRA Rx Delay, Absolute f = 1600 Hz DRR Rx Delay, Relative to DRA f = 500 – 1000 1000 – 1600 1600 – 2600 2600 – 2800 2800 – 3000 Hz 25/32 TS5070 - TS5071 Min. Typ. Max. Unit 315 s 220 s 145 ...

Page 26

... TS5070 - TS5071 NOISE Symbol Parameter NXC Transmit Noise, C Message Weighted -law Selected (note 3) 0 dBm0 = 6.4dBm NXP Transmit Noise, Psophometric Weighted A-law Selected (note 3) 0 dBm0 = 6.4dBm NRC Receive Noise, C Message Weighted -law Selected PCM code is alternating positive and negative zero ...

Page 27

... IL IL 27/ duty cycle must be used. 9.5 dB and V . For the purpose of the specification the following conditions 2 < TS5070 - TS5071 Min. Typ. Max. Unit 33 dBp 36 dBp 30 dBp dBp 25 33 dBp 36 dBp 30 dBp 25 dBp -46 dB ...

Page 28

... TS5070 - TS5071 DEFINITIONS AND TIMING CONVENTIONS DEFINITIONS V VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one. IH This parameter measured by performing a functional test at reduced clock speeds and nominal timing (i.e. not minimum setup and hold times or output strobes), with the high level of ...

Page 29

... PDIP20 TS5071N TSW5070FN Relaxed PLCC28 TS5070FN Tubes selection (Gxa, Gra, TSW5070FNTR PLCC28 TS5070FN Grag, Gxag) TSW5071N PDIP20 TS5071N TSP5070FN Special PLCC28 TS5070FN Tubes Param Page selection TSP5070FNTR PLCC28 TS5070FN for Grag/Gxag TSP5071N PDIP20 TS5071N 29/32 Tape and reel Tubes Param Page Conditions ...

Page 30

... TS5070 - TS5071 PLCC28 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 12.32 B 11.43 D 4.2 D1 2.29 D2 0.51 E 9.91 e 1.27 e3 7.62 F 0. 1.24 M1 1.143 mm MAX. MIN. 12.57 0.485 11.58 0.450 4.57 0.165 3.04 0.090 0.020 10.92 0.390 0.101 inch TYP. MAX. 0.495 0.456 0.180 0.120 0.430 0.050 0.300 0.018 0.028 0.004 0.049 0.045 30/32 ...

Page 31

... DIP20 PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.254 B 1.39 b 0. 2.54 e3 22. 31/32 mm MAX. MIN. 0.010 1.65 0.055 25.4 8.5 7.1 3.93 3.3 1.34 TS5070 - TS5071 inch TYP. MAX. 0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053 ...

Page 32

... TS5070 - TS5071 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice ...

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