TS5070FN SGS-Thomson-Microelectronics, TS5070FN Datasheet

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TS5070FN

Manufacturer Part Number
TS5070FN
Description
PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION
Manufacturer
SGS-Thomson-Microelectronics
Datasheet

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DESCRIPTION
The TS5070series are the second generationcom-
bined PCM CODEC and Filter devices optimized
for digital switching applications on subscriber and
trunk line cards.
Using advanced switched capacitor techniques the
TS5070 and TS5071 combine transmit bandpass
and receive lowpass channel filters with a com-
panding PCM encoder and decoder. The devices
are A-law and -law selectable and employ a con-
ventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programma-
ble functions may be controlled via a serial control
port.
December 1997
INCLUDING :
SLICs
WINDING SECONDARY
LSSGR SPECIFICATIONS
TERFACES
COMPLETE CODEC AND FILTER SYSTEM
– TRANSMIT AND RECEIVE PCM CHANNEL
– RECEIVE POWER AMPLIFIER DRIVES
– 4.096 MHz SERIAL PCM DATA (max)
PROGRAMMABLE FUNCTIONS :
– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB
– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB
– HYBRID BALANCE CANCELLATION FIL-
– TIME-SLOT ASSIGNMENT: UP TO 64
– 2 PORT ASSIGNMENT (TS5070)
– 6 INTERFACE LATCHES (TS5070)
– A OR -LAW
– ANALOG LOOPBACK
– DIGITAL LOOPBACK
DIRECT
SIMPLIFIES TRANSFORMER SLIC, SINGLE
STANDARD SERIAL CONTROL INTERFACE
80 mW OPERATING POWER (typ)
1.5mW STANDBY POWER (typ)
MEETS OR EXCEEDS ALL CCITT AND
TTL AND CMOS COMPATIBLE DIGITAL IN-
FILTERS
AND DECODER
300
STEPS
STEPS
TER
SLOTS/FRAME
-LAW OR A-LAW COMPANDING CODER
INTERFACE
TO
SOLID-STATE
PROGRAMMABLE CODEC/FILTER
Channel gains are programmable over a 25.4 dB
range in each direction, and a programmable filter
is included to enable Hybrid Balancing to be ad-
justed to suit a wide range of loop impedance con-
ditions.
Both transformer and active SLIC interface circuits
with real or complex termination impedances can
be balanced by this filter, with cancellation in ex-
cess of 30 dB being readily achievable when meas-
ured across the passbandagainst standardtest ter-
mination networks.
To enable COMBO IIG to interface to the SLIC con-
trol leads, a number of programmable latches are
included ; each may be configured as either an in-
put or an output. The TS5070 provides 6 latches
and the TS5071 5 latches.
COMBO 2
ORDERING NUMBERS: TS5070FN
ORDERING NUMBER:TS5071N
DIP20 (Plastic)
ND
PLCC28
GENERATION
TS5070FNTR
TS5070
TS5071
1/32

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TS5070FN Summary of contents

Page 1

... COMBO 2 GENERATION ND DIP20 (Plastic) ORDERING NUMBER:TS5071N PLCC28 ORDERING NUMBERS: TS5070FN Channel gains are programmable over a 25.4 dB range in each direction, and a programmable filter is included to enable Hybrid Balancing to be ad- justed to suit a wide range of loop impedance con- ditions. Both transformer and active SLIC interface circuits ...

Page 2

TS5070 - TS5071 TS5070 PIN FUNCTIONALITY (PLCC28) No. Name 1 GND Ground Input (+0V Analog Output Supply Input (-5V Not Connected 5 NC Not Connected 6 IL3 Digital Input or Output ...

Page 3

BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol GND GND SS SS Voltage at VFXI V Voltage at Any Digital Input IN Current at VFRO I Current at Any Digital Output O T Storage ...

Page 4

... TS5070 - TS5071 PIN CONNECTIONS PLCC28 TS5070FN POWER SUPPLY, CLOCK Pin TS5070 TS5071 Name Type GND BCLK MCLK 4/32 Function Positive Power + Supply Negative – Power Supply Ground All analog and digital signals are referenced to this pin. ...

Page 5

TRANSMIT SECTION Pin TS5070 TS5071 Name Type – ...

Page 6

TS5070 - TS5071 INTERFACE, CONTROL, RESET Pin TS5070 TS5071 Name Type FN N IL5 I/O 23 – IL4 I IL3 I IL2 I IL1 I IL0 I CCLK I 13 ...

Page 7

POWER-DOWN STATE Following a period of activity in the powered-up state the power-down state may be re-entered by writing any of the control instructions into the serial control port with the ”P” bit set to ”1” recom- mended ...

Page 8

TS5070 - TS5071 struction; and bit 0 is not used. To shift control data into COMBO IIG, CCLK must be pulsed high 8 timeswhile CS is low. Data on the CI or CI/O input is shifted into the serial input ...

Page 9

CONTROL REGISTER INSTRUCTION The first byte of a READ or WRITE instruction to the Control Register is as shown in table 1. The second byte functions are detailed in table 2. MASTER CLOCK FREQUENCY SELECTION A Master clock must be ...

Page 10

TS5070 - TS5071 This mode provides another stage of path verifica- tion by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot ...

Page 11

Alternatively, the internal time-slot assignment counters and comparators can be used to access any time-slot in a frame,using the framesync inputs as marker pulses for the beginning of transmit and receive time-slot 0. In this mode, a frame may con- ...

Page 12

TS5070 - TS5071 Table 8: Byte 2 of Receive Gain Instructions. Bit Number ...

Page 13

Figure 1 shows a simplified diagram of the local echo path for a typical application with a trans- former interface. The magnitude and phase of the local echo signal, measured are a function X of the termination ...

Page 14

TS5070 - TS5071 APPLICATION INFORMATION Figure 2 shows a typical application of the TS5070 together with a transformer SLIC. The design of the transformer is greatly simplified due to the on-chip hybrid balancecancellation filter. Only one single secondary winding is ...

Page 15

Figure 2: Transformer SLIC + COMBO IIG. TS5070 - TS5071 15/32 ...

Page 16

TS5070 - TS5071 Figure 4: Interface with L3092 + L3000 Silicon SLIC. 16/32 ...

Page 17

ELECTRICAL OPERATING CHARACTERISTICS Unless otherwise noted, limits in BOLD characters are guaranteed for - correlation with A DIGITAL INTERFACE Symbol ...

Page 18

TS5070 - TS5071 ELECTRICAL OPERATING CHARACTERISTICS (continued) POWER DISSIPATION Symbol Parameter ICC0 Power Down Current (CCLK, CI/ 0.4V 2.4V) Interface Latches set as Outputs with no load All over Inputs active, Power Amp Disabled -ISS0 Power ...

Page 19

TIMING SPECIFICATIONS (continued) PCM INTERFACE TIMING Symbol Parameter f Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz BCLK increments, TS5070 only) t Period of BCLK High (measured from V WBH t Period of BCLK Low (measured from ...

Page 20

TS5070 - TS5071 Figure 6: Delayed Data Timing (short frame mode) SERIAL CONTROL PORT TIMING Symbol Parameter f Frequency of CCLK CCLK t Period of CCLK High (measured from V WCH t Period of CCLK Low (measured from V WCL ...

Page 21

Figure 7: Control Port Timing 21/32 TS5070 - TS5071 ...

Page 22

TS5070 - TS5071 TRANSMISSION CHARACTERISTICS Unless otherwise noted, limits printed in BOLD characters are guaranteed for – =-40 Cto correlation SS ...

Page 23

AMPLITUDE RESPONSE (continued) Symbol GXAF Transmit Gain Variation with Frequency Relative to 1031.25 Hz (note 2) -19 dBm < o dBm0 < 6.4 dBm dBm0 Code 60Hz f = ...

Page 24

TS5070 - TS5071 AMPLITUDE RESPONSE (continued) Symbol GRAT Receive Gain Variation with Temperature Measure Relative to GRA -5V -17dBm < 0dBm0 < 8.1dBm CC SS GRAV Receive Gain Variation with Supply Measured Relative to GRA ...

Page 25

ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter DXA Tx Delay Absolute f = 1600 Hz DXR Tx Delay, Relative to DXA f = 500 – 600 600 – 800 800 – 1000 Hz f ...

Page 26

TS5070 - TS5071 NOISE Symbol Parameter NXC Transmit Noise, C Message Weighted -law Selected (note 3) 0 dBm0 = 6.4dBm NXP Transmit Noise, Psophometric Weighted A-law Selected (note 3) 0 dBm0 = 6.4dBm NRC Receive Noise, C Message Weighted -law ...

Page 27

DISTORTION Symbol Parameter STDX Signal to Total Distortion Transmit Sinusoidal Test Method Half Channel Level = 3dBm0 Level = -30dBm0 to 0dBm0 Level = -40dBm0 Level = -45dBm0 STDR Signal to Total Distortion Receive Sinusoidal Test Method Half Channel Level ...

Page 28

TS5070 - TS5071 DEFINITIONS AND TIMING CONVENTIONS DEFINITIONS V VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one. IH This parameter measured by performing a functional test ...

Page 29

... PDIP20 TS5071N TSW5070FN Relaxed PLCC28 TS5070FN Tubes selection (Gxa, Gra, TSW5070FNTR PLCC28 TS5070FN Grag, Gxag) TSW5071N PDIP20 TS5071N TSP5070FN Special PLCC28 TS5070FN Tubes Param Page selection TSP5070FNTR PLCC28 TS5070FN for Grag/Gxag TSP5071N PDIP20 TS5071N 29/32 Tape and reel Tubes Param Page Conditions ...

Page 30

TS5070 - TS5071 PLCC28 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 12.32 B 11.43 D 4.2 D1 2.29 D2 0.51 E 9.91 e 1.27 e3 7.62 F 0. 1.24 M1 1.143 mm MAX. MIN. 12.57 0.485 ...

Page 31

DIP20 PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.254 B 1.39 b 0. 2.54 e3 22. 31/32 mm MAX. MIN. 0.010 1.65 0.055 25.4 8.5 7.1 3.93 3.3 1.34 TS5070 - ...

Page 32

TS5070 - TS5071 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may ...

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