YGV627-V Yamaha, YGV627-V Datasheet
YGV627-V
Related parts for YGV627-V
YGV627-V Summary of contents
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... Advanced Video Display processor 3 Enhanced OUTLINE YGV627 is a VDP (Video Display Processor) that realizes higher resolution, multi-color and high speed drawing by adopting a synchronous DRAM as the video memory, while maintaining the register compatibility with YGV617B that is used for controlling the high minuteness On Screen Display (OSD). ...
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... Analog RGB output with built-in DAC (8 bits for RGB individually) Digital video input / output (6 bits for RGB individually) Equipped with sub-carrier clock output, dot clock output, sync signal output, YS and attribute output pins. [Others] Package: 176LQFP (YGV627-V) CMOS, 3.3V single power supply Operating temperature range +85 C Supplementary information: For YGV627, Application Manual that details the specifications of the device and the evaluation board (MSY627DB01/02) are available in addition to this brochure ...
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... YGV627 is connected to the external memory bus of CPU as an external I/O device video memory, SDRAM 64M bits can be connected to local memory bus of YGV627 to send bitmap image data stored in the video memory into monitor as RGB signal in accordance with display scan timing. ...
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... VSS D10 38 D11 39 D12 40 D13 41 D14 42 D15 Top view YGV627 NC 132 VSS 131 VSIN 130 HSIN 129 VDD 128 AT 127 126 YS 125 FSC 124 CSYNC 123 VSYNC HSYNC 122 121 BLANK VSS 120 DV17 ...
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... D15 D0 are in Output State in the period while both this signal and chip select signals are active. READY ( O: PULL UP, 3-state output ) This is data ready signal output to CPU. The READY signal is made low when the internal state of YGV627 is accessible. READY is a 3-state output. When CSREG or CSMEM is not active high impedance state, and when CSREG or CSMEM is active and RD or WR1, WR0 is not active, high level is outputted from READY ...
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... WAIT ( O: PULL UP, 3-state output ) This is data wait signal output to CPU. When CSREG or CSMEM is active, the level of WAIT signal is made low once with respect WR1, WR0 in accordance with the internal state of YGV627, and in accessible state, it outputs high level. When CSREG or CSMEM is not active high impedance state, and when CSREG or CSMEM is active and RD or WR1, WR0 is not active, high level is outputted from this pin ...
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... This pin outputs clock for SDRAM that is used as a video memory controlled by YGV627. Every output signal connected to SDRAM is outputted synchronizing with the rising edge of this clock. The read data from SDRAM is latched in the YGV627 at the rising edge of this clock. The clock enable pin of SDRAM should always be used in enable state. ...
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... I: PULL UP ) VR64 High level is inputted when the capacity of SDRAM that is used as a video memory controlled by YGV627 is 16M bits, or low level is inputted when the capacity is 64M bits. This signal determines the function of signal outputted from BA1, BA0, and VA11–VA0 pins. Connect with the SDRAM as specified below. ...
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... VSIN ( I: PULL UP ) This signal resets the vertical timing of CRT controller block of YGV627. When this input signal is sampled with period equal to the pulse width of horizontal sync signal, and low level is detected three times consecutively, the internal V counter is set at the first HTL timing (horizontal sync signal start timing) immediately after the moment. ...
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... HSIN ( I: PULL UP ) This signal resets the horizontal timing of CRT controller block of YGV627. The horizontal timing is set to the horizontal sync starting position at the moment this signal falls from high level to low level, and at the same time, the phase of dot clock is reset. When the built-in PLL is operated in the external sync mode, the input signal and output of HSYNC pin are locked ...
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... YGV627 SYSEL ( I: PULL UP ) This signal selects the source of reference clock to be used in the system. When low level is inputted to SYSEL, the system clock and dot clock use the same source of the clock. In this case, the common clock is inputted into DTCKIN. Therefore, there is no need to input clock into SYCKIN. When high level is inputted to SYSEL, SYCKIN pin input is used as the reference system clock independent from the dot clock ...
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... VDD, VSS ( I ) These pins supply power to digital circuit of YGV627. Connect +3 VDD and ground level to VSS. YGV627 has several VDD and VSS, all of which require power supply. Connect a bypass capacitor between VDD and VSS as a noise killer as close as possible to the pins. ...
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... YGV627 ELECTRICAL CHARACTERISTICS Absolute maximum ratings Items Supply Voltage (VDD, AVDD) Input pin voltage (DTCKIN, SYCKIN, VD15 0) other than the above Input pin voltage ( Output pin voltage Output pin current Storage temperature *1 : Value with respect to VSS (GND Recommended operating conditions Items ...
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... When the transition time is over 1 ns, the input signal IH IL (maximum value). IL Symbol Min 14.32 DTCK t 25 DCK twh 11.25 DCK twl 11.25 DCK D 45 DCK f 1 SCK t 30 SCK twh 13.5 SCK twl 13.5 SCK D 45 SCK YGV627 Typ. Max. Unit * MHz 1000 16.6 33.3 MHz 1000 1.4V ...
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... SYCKIN RESET Input Pulse Width 3 Since YGV627 produces SDRAM clock with PLL, it requires approximately 1ms after stabilization of power supply level and SYCKIN pin input clock for stabilization of clock. Moreover, in power on sequence of SDRAM, NOP *3 state of 100 s to 500 s or over is needed after stabilization of the power supply level and clock frequency. Keep these times with assert time of RESET pin (low level pulse width tWRS) ...
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... DRQ tw 20 lDAK twh 10 DAK tcy 2t SCK DAK ts 10 DMA th 10 DMA td 5 DAK th 5 CAK when WAIT and READY are used. td must be met lWR RW YGV627 Typ. Max. Unit Note + ...
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... YGV627 Write cycle ( WR1-0 control) CSREG 1 CSMEM A22-0 WR1-0 D15-0 12 READY 12 WAIT Read cycle (RD control) CSREG 1 CSMEM A22-0 RD D15-0 12 READY 12 WAIT WR1 input prohibited period CSREG CSMEM WR1 DMA access DREQ DACK D15-0 CSREG CSMEM Valid Data ...
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... Note 3: Output signals are those outputted from the following pins. BA1 0, VA11 0, VD15 0, CS, RAS, CAS, WE, DQMH, or DQML SDCLK VD[15:0] (input ) Output Signals Symbol Min. Typ. tcSDCLK 15 - twSDCLK 5 tsVD 2 thVD SDO td SDO YGV627 Max. Unit Note 1 ...
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... YGV627 Monitor interface (Measurement condition C Items No. 1 DOTCLK:delay time 2 CSYNC, VSYNC ,HSYNC, DV17 0 (out) :output hold time 3 CSYNC, VSYNC ,HSYNC, DV17 0 (out) :output delay time 4 FSC:delay time 5 HSIN, VSIN ,DV17 0 (in) :input setup time 6 HSIN, VSIN ,DV17 0 (in) :input hold time Note 1: When PLL is not used (R#22:DCKS= “ ...
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... Output hold time is defined as the period from the rise of DOTCLK to the time when output level of DAC goes out of the range of 1/2 LSB of the DOTCLK level after changing. DOTCLK Measurement circuit 20 Symbol Min. R =37 =30pF 5 L IREF= 9.38mA Hold time Settling time R,G YGV627 Typ. Max. Unit 8 bit 0 1/2 LSB 1/2 LSB ...
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... CPU External Video Equipment dot clock ¯¯¯ ¯¯¯ Vsync ¯¯¯¯¯¯ Hsync Digital RGB YGV627(AVDP3E) BA1-0 A22-0 VA11-0 D15-0 VD15-0 SYCKIN SYCKOUT SPLLFILT ¯¯¯¯¯¯¯ DVOUT ...
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... External Dimensions of Package 22 YGV627 ...
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... Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192, Japan Tel. +81-539-62-4918 Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568, Japan Tel. +81-3-5488-5431 Osaka Office 3-12-12, Minami Senba, Chuo-ku, Osaka City, Osaka, 542-0081, Japan Tel. +81-6-6252-6221 YGV627 Fax. +81-539-62-5054 Fax. +81-3-5488-5088 Fax. +81-6-6252-6229 Printed in Japan ...