IS61C1024-20H Integrated Silicon Solution, IS61C1024-20H Datasheet
IS61C1024-20H
Related parts for IS61C1024-20H
IS61C1024-20H Summary of contents
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... Easy memory expansion is provided by using two Chip Enable CE1 inputs, and CE2. The active LOW Write Enable ( controls both writing and reading of the memory. The IS61C1024 and IS61C1024L are available in 32-pin 300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type 13.4) packages. DECODER MEMORY ARRAY ...
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... IS61C1024 IS61C1024L PIN CONFIGURATION 32-Pin SOJ VCC A16 2 31 A15 A14 3 30 CE2 A12 A13 A11 A10 CE1 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 16 17 I/O3 PIN DESCRIPTIONS A0-A16 Address Inputs ...
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... IS61C1024 IS61C1024L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... SB CC CE1 Current (CMOS Inputs) CE2 0. Note address and data inputs are cycling at the maximum frequency means no input lines change. MAX IS61C1024L POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I Vcc Operating Supply Current I OUT I ...
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... Test conditions assume signal transition times less, timing reference levels of 1.5V, input pulse levels 3.0V and output loading specified in Figure 1. 2. -12 ns device for IS61C1024 only. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. ...
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... IS61C1024 IS61C1024L AC WAVEFORMS (1,2) READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID (1,3) READ CYCLE NO. 2 ADDRESS OE CE1 CE2 t LZCE1 t LZCE2 HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. 3. Address is valid prior to or coincident with OHA ...
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... The internal write time is defined by the overlap of initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. -12 ns device for IS61C1024 only Tested with HIGH ...
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... IS61C1024 IS61C1024L AC WAVEFORMS CE WRITE CYCLE NO Controlled, ADDRESS t SA CE1 CE2 WE D DATA UNDEFINED OUT WRITE CYCLE NO HIGH During Write Cycle) ADDRESS OE CE1 LOW HIGH CE2 DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of initiate a Write, but any one can go inactive to terminate the Write ...
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... IS61C1024 IS61C1024L OE WRITE CYCLE NO LOW During Write Cycle) ADDRESS OE LOW CE1 LOW HIGH CE2 DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. — 1-800-379-4774 SR028-1K 05/12/99 ( VALID ADDRESS PWE2 t HZWE HIGH DATA VALID IN ISSI ® ...
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... Plastic SOJ IS61C1024-15KI 400-mil Plastic SOJ IS61C1024-15HI sTSOP (Type I) IS61C1024-15TI TSOP (Type I) IS61C1024-20JI 300-mil Plastic SOJ IS61C1024-20KI 400-mil Plastic SOJ IS61C1024-20HI sTSOP (Type I) IS61C1024-20TI TSOP (Type I) IS61C1024-25JI 300-mil Plastic SOJ IS61C1024-25KI 400-mil Plastic SOJ IS61C1024-25HI sTSOP (Type I) IS61C1024-25TI TSOP (Type I) Order Part No ...
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... IS61C1024 IS61C1024L Integrated Silicon Solution, Inc. — 1-800-379-4774 SR028-1K 05/12/99 ISSI ISSI Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com ® ® 11 ...