IS41LV16256-35T Integrated Silicon Solution, IS41LV16256-35T Datasheet

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IS41LV16256-35T

Manufacturer Part Number
IS41LV16256-35T
Description
3.3V 256K x 16(4-MBIT) dynamic RAM with edo page mode
Manufacturer
Integrated Silicon Solution
Datasheet

Specifications of IS41LV16256-35T

Dc
9935

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IS41C16256
IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS
• JEDEC standard pinout
• Single power supply
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30
• Industrail Temperature Range -40
KEY TIMING PARAMETERS
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. J
06/29/00
(CBR), and Hidden
Parameter
Max. RAS Access Time (t
Max. CAS Access Time (t
Max. Column Address Access Time (t
Min. EDO Page Mode Cycle Time (t
Min. Read/Write Cycle Time (t
VCC
VCC
VCC
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
5V ± 10% (IS41C16256)
3.3V ± 10% (IS41LV16256)
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
RAC
CAC
)
)
RC
)
o
o
40-Pin SOJ
C to 85
PC
C to 85
)
AA
VCC
VCC
VCC
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
)
NC
NC
NC
A0
A1
A2
A3
o
o
C
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
-35
35
10
18
12
60
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
DESCRIPTION
The
high-performance CMOS Dynamic Random Access Memory. Both
products offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row with
access cycle time as short as 10ns per 16-bit word. The Byte Write
control, of upper and lower byte, makes the IS41C16256 and
IS41LV16256 ideal for use in 16 and 32-bit wide data bus systems.
These features make the IS41C16256 and IS41LV1626 ideally
suited for high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C16256 and IS41LV16256 are packaged in 40-pin
400-mil SOJ and TSOP (Type II).
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
-50
50
14
25
20
90
ISSI
IS41C16256 and IS41LV16256 are 262,144 x 16-bit
110
-60
60
15
30
25
PIN DESCRIPTIONS
A0-A8
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Unit
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ns
ns
ns
ns
ns
ISSI
JUNE 2000
®
1

Related parts for IS41LV16256-35T

IS41LV16256-35T Summary of contents

Page 1

... The Byte Write control, of upper and lower byte, makes the IS41C16256 and IS41LV16256 ideal for use in 16 and 32-bit wide data bus systems. These features make the IS41C16256 and IS41LV1626 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications ...

Page 2

... IS41C16256 IS41LV16256 FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0- CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 262,144 x 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI OE CONTROL ...

Page 3

... IS41C16256 IS41LV16256 TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write (1,2) (2) EDO Page-Mode Read 1st Cycle: 2nd Cycle: Any Cycle: EDO Page-Mode Write ...

Page 4

... Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. The IS41C16256 and IS41LV16256 has two CAS con- trols, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an iden- tical manner to the single CAS input on the other 256K x 16 DRAMs ...

Page 5

... IS41C16256 IS41LV16256 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage CC I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A Extended Temperature Industrail Temperature T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 6

... IS41C16256 IS41LV16256 ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Stand-by Current: TTL Stand-by Current: CMOS Operating Current ...

Page 7

... IS41C16256 IS41LV16256 AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC Access Time from RAS t RAC Access Time from CAS t CAC t Access Time from Column-Address AA RAS Pulse Width t RAS RAS Precharge Time t RP CAS Pulse Width ...

Page 8

... IS41C16256 IS41LV16256 AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Write Command Pulse Width WP WE Pulse Widths to Disable Outputs t WPZ Write Command to RAS Lead Time t RWL Write Command to CAS Lead Time t CWL t Write Command Setup Time WCS Data-in Hold Time (referenced to RAS) ...

Page 9

... IS41C16256 IS41LV16256 Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V ...

Page 10

... IS41C16256 IS41LV16256 READ CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE Note: is referenced from rising edge of RAS or CAS, whichever occurs last OFF RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC CAH Column ...

Page 11

... IS41C16256 IS41LV16256 EARLY WRITE CYCLE (OE = DON'T CARE) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. J 06/29/ RAS t CSH t RSH RCD CAS CLCH RAD RAL RAH CAH ASC t ACH Column t CWL t RWL ...

Page 12

... IS41C16256 IS41LV16256 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I RWC t RAS t CSH t t CAS RCD RAD RAH ASC CAH Column t RWD t t RCS CWD t AWD RAC t CAC t CLZ Open ...

Page 13

... IS41C16256 IS41LV16256 EDO-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the t specifications. PC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

Page 14

... IS41C16256 IS41LV16256 EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE I RASP t t CSH RCD CAS, CP CAS CLCH CLCH ACH ACH ASC CAH ASC Column Column t t CWL CWL t t WCS ...

Page 15

... IS41C16256 IS41LV16256 EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) RAS t t CRP RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RWD t RCS WE t RAC t t Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both 1 ...

Page 16

... IS41C16256 IS41LV16256 EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) RAS t t CRP RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RCS WE t RAC Open I RASP t CSH CAS CP CAS CAH ASC CAH Column (A) Column (B) t RCH ...

Page 17

... IS41C16256 IS41LV16256 AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE RAS-ONLY REFRESH CYCLE (OE DON'T CARE) RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. J 06/29/00 t CSH t t RCD CAS RAD ...

Page 18

... IS41C16256 IS41LV16256 CBR REFRESH CYCLE (Addresses; WE DON'T CARE RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE (WE = HIGH LOW) RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH. is referenced from rising edge of RAS or CAS, whichever occurs last. ...

Page 19

... ORDERING INFORMATION : 3.3V Commercial Range: 0⋅ ⋅ ⋅ ⋅ ⋅ 70⋅ ⋅ ⋅ ⋅ ⋅ C Speed (ns) Order Part No. Package 35 IS41LV16256-35K 400-mil SOJ IS41LV16256-35T 400-mil TSOP (Type II) 60 IS41LV16256-60K 400-mil SOJ IS41LV16256-60T 400-mil TSOP (Type II) ORDERING INFORMATION : 3.3V Industrail Range: -40⋅ ⋅ ⋅ ⋅ ⋅ 85⋅ ⋅ ⋅ ⋅ ⋅ C Speed (ns) Order Part No ...

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