IS41LV16100-50T Integrated Silicon Solution, IS41LV16100-50T Datasheet

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IS41LV16100-50T

Manufacturer Part Number
IS41LV16100-50T
Description
3.3V 1M x 16(16-MBIT) dynamic RAM with edo page mode
Manufacturer
Integrated Silicon Solution
Datasheet

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IS41C16100
IS41LV16100
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
• JEDEC standard pinout
• Single power supply:
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30
• Industrail Temperature Range -40
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
03/08/00
VCC
VCC
VCC
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
NC
NC
NC
NC
NC
— Auto refresh Mode : 1,024 cycles /16 ms
— RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode - 1,024 cycles / 128ms
— 5V ± 10% (IS41C16100)
— 3.3V ± 10% (IS41LV16100)
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
42-Pin SOJ
VCC
VCC
RAS
VCC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
NC
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
o
o
C to 85
C to 85
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
o
o
C
C
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
DESCRIPTION
The
high-performance CMOS Dynamic Random Access Memories.
These devices offer an accelerated cycle access called EDO Page
Mode. EDO Page Mode allows 1,024 random accesses within a
single row with access cycle time as short as 20 ns per 16-bit word.
The Byte Write control, of upper and lower byte, makes the
IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems.
These features make the IS41C16100and IS41LV16100 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C16100 and IS41LV16100 are packaged in a 42-pin
400-mil SOJ and 400-mil 50- (44-) pin TSOP (Type II).
KEY TIMING PARAMETERS
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Parameter
Max. RAS Access Time (t
Max. CAS Access Time (t
Max. Column Address Access Time (t
Min. EDO Page Mode Cycle Time (t
Min. Read/Write Cycle Time (t
ISSI
IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit
Data Inputs/Outputs
Address Inputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
RAC
CAC
)
)
RC
)
PC
ISSI
AA
)
)
FEBRUARY 2000
-50
50
13
25
20
84
104
-60
60
15
30
25
Unit
ns
ns
ns
ns
ns
®
1

Related parts for IS41LV16100-50T

IS41LV16100-50T Summary of contents

Page 1

... IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems. These features make the IS41C16100and IS41LV16100 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-mil SOJ and 400-mil 50- (44-) pin TSOP (Type II ...

Page 2

... IS41C16100 IS41LV16100 FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0- CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 1,048,576 x 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI OE CONTROL ...

Page 3

... IS41C16100 IS41LV16100 TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) (1,2) Read-Write (2) EDO Page-Mode Read 1st Cycle: 2nd Cycle: Any Cycle: (1) EDO Page-Mode Write ...

Page 4

... IS41C16100 IS41LV16100 Functional Description The IS41C16100 and IS41LV16100 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS) ...

Page 5

... IS41C16100 IS41LV16100 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage CC I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A Extendedl Operation Temperature Industrial Operationg Temperature T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 6

... IS41C16100 IS41LV16100 ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Standby Current: TTL Standby Current: CMOS Operating Current ...

Page 7

... IS41C16100 IS41LV16100 (1,2,3,4,5,6) AC CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC Access Time from RAS t RAC Access Time from CAS t CAC t Access Time from Column-Address AA RAS Pulse Width t RAS RAS Precharge Time t RP CAS Pulse Width ...

Page 8

... IS41C16100 IS41LV16100 AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Write Command Pulse Width WP WE Pulse Widths to Disable Outputs t WPZ Write Command to RAS Lead Time t RWL Write Command to CAS Lead Time t CWL t Write Command Setup Time WCS Data-in Hold Time (referenced to RAS) ...

Page 9

... IS41C16100 IS41LV16100 AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%) One TTL Load and 50 pF (Vcc = 3.3V ±10%) Input timing reference levels Output timing reference levels Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured ...

Page 10

... IS41C16100 IS41LV16100 READ CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE Note: is referenced from rising edge of RAS or CAS, whichever occurs last OFF RAS t CSH t RSH t t CAS RCD RAD RAL t t RAH ASC Column t RCS t AA ...

Page 11

... IS41C16100 IS41LV16100 EARLY WRITE CYCLE (OE = DON'T CARE) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. F 03/08/ RAS t CSH t RSH t t CAS RCD RAD RAL RAH ASC CAH t ACH Column t CWL t RWL t WCR ...

Page 12

... IS41C16100 IS41LV16100 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I RWC t RAS t CSH t t CAS RCD RAD RAH CAH ASC Column t RWD t t RCS CWD t AWD RAC t CAC t CLZ Open ...

Page 13

... IS41C16100 IS41LV16100 EDO-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the t specifications. PC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

Page 14

... IS41C16100 IS41LV16100 EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE I RASP t CSH RCD CAS, CP CAS CLCH CLCH ACH ACH ASC CAH ASC Column Column t t CWL CWL t t WCS ...

Page 15

... IS41C16100 IS41LV16100 EDO-PAGE-MODE READ-WRITE CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the t specifications. PC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

Page 16

... IS41C16100 IS41LV16100 EDO-PAGE-MODE READ-EARLY-WRITE CYCLE RAS CRP RCD UCAS/LCAS ASR t RAD t t ASC RAH ADDRESS Row t RCS WE t RAC t CAC Open I (Psuedo READ-MODIFY WRITE) t RASP CSH CAS CP CAS CAH ASC CAH Column (A) Column ( ...

Page 17

... IS41C16100 IS41LV16100 AC WAVEFORMS (With WE-Controlled Disable) READ CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE RAS-ONLY REFRESH CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. F 03/08/00 t CSH t t RCD CAS RAD t t RAH ASC Column ...

Page 18

... IS41C16100 IS41LV16100 CBR REFRESH CYCLE (Addresses; WE DON'T CARE) RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE (1) RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH. is referenced from rising edge of RAS or CAS, whichever occurs last. ...

Page 19

... IS41C16100 IS41LV16100 ORDERING INFORMATION : 5V Commercial Range: 0° ° ° ° ° 70° ° ° ° ° C Speed (ns) Order Part No. Extended Range: -30° ° ° ° ° 85° ° ° ° ° C Speed (ns) Order Part No. Industrial Range: -40° ° ° ° ° 85° ° ° ° ° C Speed (ns) Order Part No. Integrated Silicon Solution, Inc. — ...

Page 20

... IS41LV16100-50TE 400-mil TSOP (Type II) 60 IS41LV16100-60KE 400-mil SOJ IS41LV16100-60TE 400-mil TSOP (Type II) Package 50 IS41LV16100-50KI 400-mil SOJ IS41LV16100-50TI 400-mil TSOP (Type II) 60 IS41LV16100-60KI 400-mil SOJ IS41LV16100-60TI 400-mil TSOP (Type II) Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® ISSI ® ...

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