AM49PDL127BH SPANSION, AM49PDL127BH Datasheet
AM49PDL127BH
Related parts for AM49PDL127BH
AM49PDL127BH Summary of contents
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... Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary ...
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... ADVANCE INFORMATION Am49PDL127BH/Am49PDL129BH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit ( 16-Bit) CMOS Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — ...
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... Standby: 70 µA maximum — Deep power-down standby: 5 µA CE1s# and CE2ps Chip Select Power down features using CE1s# and CE2ps Data retention supply voltage: 2.7 to 3.3 volt Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) 8-word page mode access level CC Am49PDL127BH/Am49PDL129BH December 16, 2003 ...
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... AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am49PDL127BH/Am49PDL129BH de ...
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... DQ3: Sector Erase Timer ....................................................... 56 Table 17. Write Operation Status ................................................... 57 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 58 Figure 9. Maximum Negative Overshoot Waveform ...................... 58 Figure 10. Maximum Positive Overshoot Waveform...................... 58 ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 59 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 11. Test Setup.................................................................... 61 Figure 12. Input Waveforms and Measurement Levels ................. 61 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 62 CE#1ps Timing ....................................................................... 62 Am49PDL127BH/Am49PDL129BH December 16, 2003 ...
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... Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 80 pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . 81 pSRAM Power on and Deep Power Down . . . . . 81 Figure 32. Deep Power-down Timing............................................. 81 Figure 33. Power-on Timing........................................................... 81 pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 82 Figure 34. Read Address Skew ..................................................... 82 Figure 35. Write Address Skew...................................................... 82 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 83 TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 83 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 84 Am49PDL127BH/Am49PDL129BH 5 ...
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... CE2ps Am49PDL127BH/Am49PDL129BH Flash Memory RY/BY# 128 MBit Flash Memory DQ15 to DQ0 MBit DQ15 to DQ0 Pseudo SRAM Am49PDL127BH/Am49PDL129BH Pseudo SRAM DQ15 to DQ0 December 16, 2003 ...
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... DQ4 DQ13 DQ15 DQ12 DQ7 DQ11 NC DQ5 DQ14 exposed to temperatures above 150°C for prolonged periods of time. Am49PDL127BH/Am49PDL129BH A10 NC Pseudo B10 SRAM Only NC Flash Only Shared F10 NC G10 NC SS L10 NC M10 NC 7 ...
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... DQ12 DQ7 DQ11 NC DQ5 DQ14 integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am49PDL127BH/Am49PDL129BH A10 NC Pseudo B10 SRAM Only NC Flash Only D9 Shared A15 E9 A21 F9 F10 A22 NC G9 G10 A16 ...
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... Device Ground (Common Pin Not Connected Internally December 16, 2003 LOGIC SYMBOL 21 A20–A0 A21 A22 (PDL127 Only) CE#f1 CE#f2 (PDL129 Only) CE#1ps CE2ps OE# WE# WP#/ACC , the device is IH RESET# , UB#s OL LB#s , the highest IL , these sector IH Am49PDL127BH/Am49PDL129BH 16 DQ15–DQ0 RY/BY# 9 ...
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... DQ12 DQ7 DQ11 A25 or V DQ5 DQ14 CCQ CE CCQ CCQ CCQ Am49PDL127BH/Am49PDL129BH LEGEND A9 A10 B10 Data Storage RY/BY# 1st RAM D9 CE#1 E9 2nd RAM A15 FASL Standard F9 MCP Packages 7.0 x 9.0 mm A21 8.0 x 10.0 mm 8 9.0 x 12.0 mm ...
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... MCP will be a subset of the ballout dia- gram shown. In some cases, there may be outrigger balls in loca- tions outside the grid shown. Do not connect these outrigger balls to any signal. For further information re- garding the look-ahead ballout, contact the appropri- ate AMD or Fujitsu sales office. Am49PDL127BH/Am49PDL129BH 11 ...
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... See “Product Selector Guide” on page 5. PROCESS TECHNOLOGY H = 0.13 µm PSEUDO SRAM DEVICE DENSITY Mbits CONTROL PINS Flash Flash Order Number Am49PDL127BH66I Am49PDL127BH85I Am49PDL129BH66I Am49PDL129BH85I Am49PDL127BH/Am49PDL129BH ° C) Valid Combinations Package Marking T, S M490000028 T, S M490000029 T, S M490000030 T, S M490000031 December 16, 2003 ...
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... The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am49PDL127BH/Am49PDL129BH 13 ...
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... IL IH unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V be unprotected. 7. Data will be retained in pSRAM. 8. Data will be lost in pSRAM. 9. Both CE#f1 inputs may be held low for this operation. Am49PDL127BH/Am49PDL129BH UB#s WP#/ DQ7– (Note RESET# ACC DQ0 3) 3) (Note 4) ...
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... Table 3. Bank Select (PDL129H) Bank Bank A Bank B Bank C Bank D Table 4. Bank Select (PDL127H and ACC CE Bank Bank A ), the reasser- Bank B IH Bank C . Here again, CE Bank D Am49PDL127BH/Am49PDL129BH Table 2. Page Select ...
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... Note that during automatic sleep mode, OE# must current to the stated sleep mode specification. I when not in CC the DC Characteristics table represents the automatic sleep mode current specification. Am49PDL127BH/Am49PDL129BH ± 0.3 V. (Note that this is a more restricted .) If CE#f1, CE#f2 (PDL129 IH , but not within for read access when the ...
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... SET# parameters and to Figure 16 for the timing dia- gram. Output Disable Mode When the OE# input disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Am49PDL127BH/Am49PDL129BH (during Embedded Algorithms). The sys- (not during Embedded Algo- READY after the RE- RH ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127BH/Am49PDL129BH Address Range (x16) 4 000000h–000FFFh 4 001000h–001FFFh 4 002000h–002FFFh 4 003000h–003FFFh 4 004000h–004FFFh 4 005000h–005FFFh 4 006000h–006FFFh 4 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127BH/Am49PDL129BH 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127BH/Am49PDL129BH 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127BH/Am49PDL129BH 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127BH/Am49PDL129BH 4C0000h–4C7FFFh 4C8000h–4CFFFFh 4D0000h–4D7FFFh 4D8000h–4DFFFFh 4E0000h–4E7FFFh 4E8000h–4EFFFFh 4F0000h–4F7FFFh 4F8000h–4FFFFFh 500000h–507FFFh 508000h–50FFFFh 510000h–517FFFh 518000h–51FFFFh 520000h–527FFFh 528000h–52FFFFh 530000h– ...
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... Am49PDL127BH/Am49PDL129BH 600000h–607FFFh 608000h–60FFFFh 610000h–617FFFh 618000h–61FFFFh 620000h–627FFFh 628000h–62FFFFh 630000h–637FFFh 638000h–63FFFFh 640000h–647FFFh 648000h–64FFFFh 650000h–657FFFh 658000h–65FFFFh 660000h–667FFFh 668000h–66FFFFh 670000h–677FFFh 678000h–67FFFFh 680000h– ...
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... Am49PDL127BH/Am49PDL129BH Address Range (x16) 700000h–707FFFh 708000h–70FFFFh 710000h–717FFFh 718000h–71FFFFh 720000h–727FFFh 728000h–72FFFFh 730000h–737FFFh 738000h–73FFFFh 740000h–747FFFh 748000h–74FFFFh 750000h–757FFFh 758000h–75FFFFh 760000h–767FFFh 768000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127BH/Am49PDL129BH Sector Size Address Range (x16) (Kwords) 4 000000h–000FFFh 4 001000h–001FFFh 4 002000h–002FFFh 4 003000h–003FFFh 4 004000h–004FFFh 4 005000h–005FFFh 4 006000h–006FFFh 4 007000h–007FFFh 32 008000h–00FFFFh 32 010000h–017FFFh 32 018000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127BH/Am49PDL129BH 32 100000h–107FFFh 32 108000h–10FFFFh 32 110000h–117FFFh 32 118000h–11FFFFh 32 120000h–127FFFh 32 128000h–12FFFFh 32 130000h–137FFFh 32 138000h–13FFFFh 32 140000h–147FFFh 32 148000h–14FFFFh 32 150000h–157FFFh 32 158000h–15FFFFh 32 160000h–167FFFh 32 168000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127BH/Am49PDL129BH 32 240000h–247FFFh 32 248000h–24FFFFh 32 250000h–257FFFh 32 258000h–25FFFFh 32 260000h–267FFFh 32 268000h–26FFFFh 32 270000h–277FFFh 32 278000h–27FFFFh 32 280000h–287FFFh 32 288000h–28FFFFh 32 290000h–297FFFh 32 298000h–29FFFFh 32 2A0000h–2A7FFFh 32 2A8000h– ...
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... Am49PDL127BH/Am49PDL129BH 32 380000h–387FFFh 32 388000h–38FFFFh 32 390000h–397FFFh 32 398000h–39FFFFh 32 3A0000h–3A7FFFh 32 3A8000h–3AFFFFh 32 3B0000h–3B7FFFh 32 3B8000h–3BFFFFh 32 3C0000h–3C7FFFh 32 3C8000h–3CFFFFh 32 3D0000h–3D7FFFh 32 3D8000h–3DFFFFh 32 3E0000h–3E7FFFh 32 3E8000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127BH/Am49PDL129BH 32 000000h–007FFFh 32 008000h–00FFFFh 32 010000h–017FFFh 32 018000h–01FFFFh 32 020000h–027FFFh 32 028000h–02FFFFh 32 030000h–037FFFh 32 038000h–03FFFFh 32 040000h–047FFFh 32 048000h–04FFFFh 32 050000h–057FFFh 32 058000h–05FFFFh 32 060000h–067FFFh 32 068000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127BH/Am49PDL129BH 32 0C0000h–0C7FFFh 32 0C8000h–0CFFFFh 32 0D0000h–0D7FFFh 32 0D8000h–0DFFFFh 32 0E0000h–0E7FFFh 32 0E8000h–0EFFFFh 32 0F0000h–0F7FFFh 32 0F8000h–0FFFFFh 32 100000h–107FFFh 32 108000h–10FFFFh 32 110000h–117FFFh 32 118000h–11FFFFh 32 120000h–127FFFh 32 128000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127BH/Am49PDL129BH 32 200000h–207FFFh 32 208000h–20FFFFh 32 210000h–217FFFh 32 218000h–21FFFFh 32 220000h–227FFFh 32 228000h–22FFFFh 32 230000h–237FFFh 32 238000h–23FFFFh 32 240000h–247FFFh 32 248000h–24FFFFh 32 250000h–257FFFh 32 258000h–25FFFFh 32 260000h–267FFFh 32 268000h– ...
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... SecSi Sector Area Customer-Lockable Area Address Range 000000h-00003Fh Am49PDL127BH/Am49PDL129BH 32 300000h–307FFFh 32 308000h–30FFFFh 32 310000h–317FFFh 32 318000h–31FFFFh 32 320000h–327FFFh 32 328000h–32FFFFh 32 330000h–337FFFh 32 338000h–33FFFFh 32 340000h–347FFFh 32 348000h–34FFFFh 32 350000h–357FFFh 32 358000h– ...
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... Kwords SA268 128 (4x32) Kwords SA269 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords Sector/ Sector Block Size 128 (4x32) Kwords Am49PDL127BH/Am49PDL129BH 100000XXXXX 128 (4x32) Kwords 100001XXXXX 128 (4x32) Kwords 100010XXXXX 128 (4x32) Kwords 100011XXXXX 128 (4x32) Kwords 100100XXXXX ...
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... SA263 128 (4x32) Kwords SA264 128 (4x32) Kwords SA265 128 (4x32) Kwords SA266 128 (4x32) Kwords SA267 128 (4x32) Kwords SA268 128 (4x32) Kwords SA269 Am49PDL127BH/Am49PDL129BH Sector/ CE#f1 CE#f2 A21–A12 Sector Block Size 0 1 11110XXXXX 128 (4x32) Kwords 0 1 11111XXXXX 128 (4x32) Kwords ...
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... These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. This allows software to easily protect sectors against inadvertent changes yet does Am49PDL127BH/Am49PDL129BH 35 ...
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... IL Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differ- Am49PDL127BH/Am49PDL129BH PPB Lock Sector State Unprotected—PPB and DYB are 0 changeable Unprotected— ...
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... Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. Am49PDL127BH/Am49PDL129BH on the WP#/ACC pin, the de the WP#/ACC pin, the de- ...
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... The proce- dure requires high voltage (V RESET# pin. Refer to Figure 1 for details on this pro- cedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. Am49PDL127BH/Am49PDL129BH ) to be placed on the ID December 16, 2003 ...
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... PLSCNT = 1000? Yes Remove V from RESET# Write reset command Sector Unprotect complete Device failed Sector Unprotect Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms Am49PDL127BH/Am49PDL129BH START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors ...
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... Follow the SecSi Sector protection algorithm as shown in Figure 3. This allows in-system protection of the SecSi Sector Region without raising any de- vice pin to a high voltage. Note that this method is only applicable to the SecSi Sector. Am49PDL127BH/Am49PDL129BH December 16, 2003 ...
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... SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent program- ming of the SecSi Sector memory area. Once set, the Am49PDL127BH/Am49PDL129BH SecSi Sector Entry SecSi Sector Protection SecSi Sector Exit 41 ...
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... For further information, please refer to the CFI Specifi- LKO cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna tively, contact an AMD representative for copies of these documents. Am49PDL127BH/Am49PDL129BH or WE initiate and OE during power up, IL ...
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... Max. timeout for byte/word write 2 times typical N Max. timeout for buffer write 2 times typical Max. timeout per individual block erase 2 N Max. timeout for full chip erase 2 times typical (00h = not supported) Am49PDL127BH/Am49PDL129BH N µs µ (00h = not supported times typical ...
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... CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Am49PDL127BH/Am49PDL129BH N December 16, 2003 ...
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... Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported Supported Bank Organization 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am49PDL127BH/Am49PDL129BH 45 ...
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... The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Am49PDL127BH/Am49PDL129BH Table 4 shows the address range December 16, 2003 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the table in the AC Characteristics section for parameters, and Figures 17 Am49PDL127BH/Am49PDL129BH any operation HH Erase and Program Operations and 18 for timing diagrams. 47 ...
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... Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading Am49PDL127BH/Am49PDL129BH December 16, 2003 ...
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... The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no pro- visions for entering the 2-cycle unlock cycle, the pass- Am49PDL127BH/Am49PDL129BH Autoselect Command Sequence sections 49 ...
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... Exiting the DYB Write command is accom- plished by writing the Read/Reset command. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- Am49PDL127BH/Am49PDL129BH -level SecSi Sector CC December 16, 2003 ...
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... Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. Am49PDL127BH/Am49PDL129BH 51 ...
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... Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. Am49PDL127BH/Am49PDL129BH Data Addr Data Addr Data ...
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... Following the final cycle of the command sequence, the user must write the first three cycles of the Autoselect command and then write a Reset command. 18. If checking the DYB status of sectors in multiple banks, the user must follow Note 17 before crossing a bank boundary. Am49PDL127BH/Am49PDL129BH Data Addr Data Addr ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 7. Data# Polling Algorithm Am49PDL127BH/Am49PDL129BH Figure 7 START Addr = VA Yes No ...
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... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 8. Toggle Bit Algorithm Am49PDL127BH/Am49PDL129BH Figure 22 section shows the tog- START Read Byte (DQ7– ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 17 shows the status of DQ3 relative to the other status bits. Am49PDL127BH/Am49PDL129BH December 16, 2003 ...
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... The device outputs array data if the system addresses a non-busy bank. December 16, 2003 Table 17. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am49PDL127BH/Am49PDL129BH DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... Component manufacturer contact information is listed in the Span- sion MCP Qualification Report, when available. The Spansion Flash memory Qualification Database and Spansion MCP Qualification Report are available from AMD and Fujitsu sales offices. Am49PDL127BH/Am49PDL129BH Overshoot Waveform 20 ns ...
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... Embedded Erase or Embedded Program progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for t current is 1 µ CCmax 6. Not 100% tested. Am49PDL127BH/Am49PDL129BH Min Typ Max Unit ±1.0 µA 35 µA 35 µA ±1.0 µA ...
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... Cycle time = Min mA, 100% IO duty, CE#1ps = V , CE#2ps = Min 1 –0 CE# –0.2 V, CCS CE2 = V = 0.2 V CCS CE2 = 0.2 V Am49PDL127BH/Am49PDL129BH Min Typ Max Unit –1.0 1.0 –1 –0.3 0.4 (Note 0.3 CC 2.4 (Note 2) December 16, 2003 µA µ ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am49PDL127BH/Am49PDL129BH 66, 85 Unit 1 TTL gate 0.0–3 ...
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... CE#1ps Timing Parameter JEDEC Std Description — t CE#1ps Recover Time CCR CE#1ps CE2ps Figure 13. Timing Diagram for Alternating — t CCR Between Pseudo SRAM and Flash Am49PDL127BH/Am49PDL129BH Test Setup All Speeds Unit Min CCR December 16, 2003 ...
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... CE#f1 Read Toggle and Data# Polling 5. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V bus driven CE#f2 Valid CE#f1/CE#f2 transitions: (CE#f1= V (CE#f1 (CE#f1 Am49PDL127BH/Am49PDL129BH Speed Options 66 85 Min 65 85 Max Max Max 25 30 Max ...
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... Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 14. Read Operation Timings Same Page PACC t ACC Qa ; During CE#f2 transitions, CE#f1 Am49PDL127BH/Am49PDL129BH HIGH PACC PACC December 16, 2003 ...
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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 16. Reset Timings Am49PDL127BH/Am49PDL129BH All Speed Options Unit µs 20 500 ns 500 µ ...
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... Write Recovery Time from RY/BY Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Word Am49PDL127BH/Am49PDL129BH Speed 66 85 Unit Min Min 05 ns Min ...
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... WPH A0h t BUSY is the true data at the program address. OUT IH. Figure 17. Program Operation Timings Am49PDL127BH/Am49PDL129BH Read Status Data (last two cycles WHWH1 Status D OUT VHH 67 ...
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... Figure 19. Chip/Sector Erase Operation Timings SADD 555h for chip erase WPH 55h 30h 10 for Chip Erase . IH Am49PDL127BH/Am49PDL129BH Read Status Data WHWH2 In Complete Progress t t BUSY RB December 16, 2003 ...
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... DH OH Valid Valid In Out t SR/W Read Cycle ACC Complement Complement Status Data Status Data Am49PDL127BH/Am49PDL129BH Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data 69 ...
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... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 23. DQ2 vs. DQ6 Am49PDL127BH/Am49PDL129BH Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read December 16, 2003 ...
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... CE#f1 or CE#f2 (PDL129 only) WE# RY/BY# Figure 24. Temporary Sector Unprotect Timing Diagram December 16, 2003 Min Min Min Min VIDR Program or Erase Command Sequence t RSP Am49PDL127BH/Am49PDL129BH All Speed Options Unit 500 ns 250 ns µs 4 µ ...
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... For PDL129 during CE#f1 transitions the other CE#f1 pin = V Figure 25. Sector/Sector Block Protect and Valid* 60h 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am49PDL127BH/Am49PDL129BH Valid* Valid* Verify 40h Status December 16, 2003 ...
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... Word or Byte (Note Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. December 16, 2003 Am49PDL127BH/Am49PDL129BH Speed 66 85 Unit Min Min 0 ns ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am49PDL127BH/Am49PDL129BH PA DQ7# D OUT December 16, 2003 ...
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... ACC Indeterminate t OEE t COE 3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Figure 27. Pseudo SRAM Read Cycle Am49PDL127BH/Am49PDL129BH Speed 66 85 Min 70 85 Max 70 85 Max 70 85 Max 25 Max 25 ...
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... OEE AOH AOH D D OUT OUT Maximum 8 words Figure 28. Page Read Timing 3. If CE#f1, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Am49PDL127BH/Am49PDL129BH Fixed High AOH OUT ...
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... Min Min Min Min Min Min Min Max Min Min Min Min Min Min ODW High Valid Data In Am49PDL127BH/Am49PDL129BH Speed Unit ...
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... If OE# is high during the write cycle, the outputs will remain at high impedance. Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ODW t COE t DS Valid Data In Am49PDL127BH/Am49PDL129BH t WR High (Note 1) December 16, 2003 ...
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... If OE# is high during the write cycle, the outputs will remain at high impedance. December 16, 2003 COE t ODW Valid Data In Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control Am49PDL127BH/Am49PDL129BH t WR High ...
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... V, 1,000,000 cycles. All values are subject to change. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT Test Conditions Am49PDL127BH/Am49PDL129BH Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec Excludes system level µs overhead (Note 5) µs sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... Test Setup CS1#ps ≥ V – 0.2 V (Note 3.0 V, CE1#ps ≥ (Note 1) – 0.2 V (CE1#s controlled) or CE2ps ≤ 0.2 V (CE2ps controlled). t DPD Figure 32. Deep Power-down Timing t CHC t CH Figure 33. Power-on Timing Am49PDL127BH/Am49PDL129BH Min Typ Max 2.7 3.3 – 0.2 V 1.0 70 (Note 2) 0 300 Unit V µ ...
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... RC min Figure 34. Read Address Skew min occur for a period greater than 10 µs, at least one valid address RC over 10 µ min t WC min Figure 35. Write Address Skew min occur for a period greater than 10 µs, at least one valid address WC Am49PDL127BH/Am49PDL129BH December 16, 2003 ...
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... IN THE OUTER ROW E/2 BALL PITCH 8. "+" INDICATES THE THEORETICAL CENTER OF SOLDER BALL PLACEMENT DEPOPULATED BALLS. DEPOPULATED SOLDER BALLS 9. NOT USED. 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am49PDL127BH/Am49PDL129BH ...
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... Table 16, Sector Protection Command Definitions Corrected number of cycles for SecSi Protection Bit specifica- WEH Status, PPMLB Status, and SPMLB Status from cycles. For these command sequences, inserted a cycle before the final read cycle (RD0). ESD Immunity Added section. Am49PDL127BH/Am49PDL129BH December 16, 2003 ...