LAN91C94 SMSC Corporation, LAN91C94 Datasheet
LAN91C94
Available stocks
Related parts for LAN91C94
LAN91C94 Summary of contents
Page 1
... Four Direct Driven LEDs for Status/ Diagnostics Software Drivers Uses Certified LAN9000 Drivers Which Operate with Every Major Network Operating System Software Driver Compatible with LAN91C92 and LAN91C100 (100 Mbps) Controllers in ISA Mode Software Driver Utilizes Full Capability of 32 Bit Microprocessor LAN91C94 PRELIMINARY ...
Page 2
FEATURES ........................................................................................................................................ 1 PIN CONFIGURATION ....................................................................................................................... 3 GENERAL DESCRIPTION .................................................................................................................. 5 OVERVIEW ........................................................................................................................................ 5 DESCRIPTION OF PIN FUNCTIONS ................................................................................................. 8 FUNCTIONAL DESCRIPTION .......................................................................................................... 20 THEORY OF OPERATION ............................................................................................................... 66 FUNCTIONAL DESCRIPTION OF THE BLOCKS .............................................................................. 78 BOARD SETUP INFORMATION ....................................................................................................... ...
Page 3
... RECP 85 TPERXN 86 TPERXP 87 AVSS 88 AVSS 89 RBIAS 90 100 Pin QFP AVDD 91 nXENDEC 92 nEN16 93 VSS 94 nROM/nPCMCIA 95 XTAL1 96 XTAL2 97 IOS0 98 IOS1 99 VDD 100 PIN CONFIGURATION LAN91C94 3 50 RAMVDD 49 A19/nCE1 48 A18 47 A17 46 A16 45 A15 44 A14 43 A13 42 A12 41 A11/nFCS 40 VDD 39 A10/nFWE ...
Page 4
... ENEEP 1 EEDO/SDOUT 2 EEDI 3 EECS 4 EESK 5 VSS LAN91C94 D9 8 D10 9 D11 10 VDD 11 100 Pin TQFP D12 12 D13 13 D14 14 D15 15 VSS 16 and VTQFP INTR0/nIREQ 17 INTR1/nINPACK 18 VDD 19 INTR2 20 INTR3 21 RAMVSS 22 nIOCS16 23 nSBHE/nCE2 24 BALE/nWE ...
Page 5
... AUI interface. LAN91C94 integrates transceiver as well as the link integrity test Unit) functions. The LAN91C94 is a true 10BASE-T single chip able to interface a system or a local bus. Directly-driven LEDs for installation and run- are time diagnostics are provided, as well as 802.3 All other statistics gathering management ...
Page 6
... EEPROM for IEEE address storage. PCMCIA I/O ignores address lines A4- A15 and relies on the PCMCIA host, decoding for the slot. nROM/nPCMCIA, on LAN91C94, is left open with a pullup for ISA mode. This pin is sampled at the end of RESET. If found low, the LAN91C94 is configured for PCMCIA mode. 6 ...
Page 7
ISA vs. PCMCIA PIN GROUPS FUNCTION SYSTEM ADDRESS BUS SYSTEM DATA BUS SYSTEM CONTROL BUS SERIAL EEPROM CRYSTAL OSC. POWER GROUND 10BASE-T interface ISA PCMCIA A0-9 A0-9 A10 nFWE A11 nFCS A12-14 A15 A15 A16-18 A19 nCE1 AEN nREG D0-15 ...
Page 8
... PCMCIA mode. For ISA operation, this pin is left open and is used as a ROM chip select output. It turns active when MEMR* is low and the address bus contains a valid ROM address. In ISA mode the LAN91C94 is pin compatible with the LAN91C92 A0-9 I Input - Input address lines 0 through 9 ...
Page 9
... PCMCIA - Card Enable 2 input. To select card on odd byte accesses OD24 with ISA - Output - Optionally used by the pullup LAN91C94 to extend host cycles PCMCIA - Output - Optionally used by the LAN91C94 to extend host cycles D0-15 I/O24 Bidirectional - 16 bit data bus to access the registers. The data bus has weak internal pullups ...
Page 10
PIN NUMBER VTQFP/ QFP TQFP NAME SYMBOL 67 65 Reset RESET 27 25 Address BALE/nWE Latch 19 17 Interrupt INTR0/ nIREQ 20 18 INTR1/ nINPACK 22,23 20,21 Interrupt INTR2-3 BUFFER TYPE DESCRIPTION IS with Input - Active high Reset. This ...
Page 11
... AEN is low and A4-A15 decode to the LAN91C94 address programmed into the high byte of the Base Address Register PCMCIA - Active low output asserted whenever the LAN91C94 bit mode, COR0 bit is high, and REG* is low IS with Input - Active low read strobe to ...
Page 12
... Must be connected to ground if no serial EEPROM is used I with Input - When low the LAN91C94 is pullup configured for 16 bit bus operation. If left open the LAN91C94 works in 8 bit bus mode. 16 bit configuration can also be EEPROM, software initialization of the CONFIGURATION REGISTER, and PCMCIA configuration space ...
Page 13
... Used in combination with TPETXP and TPETXN to generate the 10BASE-T transmit pre-distortion I with INTERNAL pullup input. It keeps the LAN91C94 in powerdown mode when high (open). Must be low for normal operation EXTERNAL ENDEC - Transmit clock input from external ENDEC. Analog A 22kohm 1% resistor should be ...
Page 14
... Input buffer with Schmitt Trigger Hysteresis Iclk Clock input buffer DC levels and conditions defined in the DC Electrical Characteristics section. BUFFER TYPE I with When tied low, the LAN91C94 is pullup configured for EXTERNAL ENDEC. When tied high or left open, the LAN91C94 encoder/decoder VDD +5V power supply pins ...
Page 15
Table 1 - Bus Transactions in ISA Mode 8 BIT MODE ((nEN16=1) (16BIT=0)) 16 BIT MODE otherwise Table 2 - Bus Transactions in PCMCIA Mode A0 8 BIT MODE 0 ((IOis8=1) + (nEN16=1).(16BIT=0 BIT MODE 0 otherwise ...
Page 16
FIGURE 1 – SYSTEM DIAGRAM FOR ISA BUS WITH BOOT PROM 16 ...
Page 17
... DATA BUS ADDRESS BUS BUS INTERFACE CONTROL FIGURE 2 – LAN91C94 INTERNAL BLOCK DIAGRAM ENDEC ARBITER CSMA/ TWISTED PAI R TRANSCEIVER RAM 17 AUI 10BASE-T ...
Page 18
... FIGURE 3A - LAN91C94 PCMCIA 10BASE-T/AUI SCHEMATIC 18 ...
Page 19
... LAN91C94 ISA 10BASE-T/COAX SCHEMATIC 19 ...
Page 20
... The I/O space is 16 bits wide. Provisions for 8 bit systems are handled by the bus interface. In the system memory space kbytes are decoded by the LAN91C94 as expansion ROM. The ROM expansion area is 8 bits wide. Device configuration is done using a serial EEPROM, with support for modifications to the EEPROM at installation time ...
Page 21
... The LAN91C94 provides a 16 bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter. RAM memory is managed by the MMU. word accesses to the RAM are supported. If the system to SRAM bandwidth is insufficient the LAN91C94 will automatically IOCHRDY line for flow control ...
Page 22
FIGURE 4 – MAPPING AND PAGING VS. RECEIVE AND TX AREA 22 ...
Page 23
FIGURE 5 – TRANSMIT QUEUES AND MAPPING 23 ...
Page 24
FIGURE 6 – RECEIVE QUEUE AND MAPPING 24 ...
Page 25
... FIGURE 7 – LAN91C94 INTERNAL BLOCK DIAGRAM WITH DATA PATH 25 ...
Page 26
FIGURE 8 – LOGICAL ADDRESS GENERATION AND RELEVENT REGISTERS 26 ...
Page 27
PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the TRANSMIT and RECEIVE areas. The first word is reserved for the status word, the next bit15 RAM OFFSET (DECIMAL RESERVED 4 2046 Max CONTROL ...
Page 28
... CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C94 treated transparently as data for both transmit and receive operations. CONTROL BYTE The CONTROL BYTE always resides on the high byte of the last word ...
Page 29
RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory not available as a register. HIGH ALGN BROD BYTE ERR CAST LOW BYTE 5 ALGNERR Frame had alignment error. BRODCAST Receive ...
Page 30
... INDIVID UAL 6 COUNTER ADDRESS 8 MIR GENER AL A MCR PURPOSE RESERVED CONTROL C E BANK SELECT REGISTER Non vola ti le, stored i n EEPROM. FIGURE 10 – LAN91C94 REGISTERS 30 BANK2 BANK3 MMU COMMAND PNR ARR MULTICAST FIFO PORTS TABLE POINTER DATA MGMT DATA REVISION INTERRUPT ...
Page 31
... ATTRIBUTE MEMORY SPACE (PCMCIA mode only) In PCMCIA mode, the attribute memory space is an eight bit space decoded by the LAN91C94 using addresses A0-9, A15 along OFFSET 8000 CARD OPTION REGISTER This register is used to enable the PCMCIA card, allow programming of the external attribute memory, and to generate soft reset ...
Page 32
... CONFIGURATION/STATUS REGISTER 0 0 IOis8 IOis8 - This bit when set, indicates to the LAN91C94 that the host is limited to 8 bit interface. In PCMCIA mode the LAN91C94 will operate in 8 bit mode whenever ((IOis8 (nEN16 = 1) . (16BIT = 0)). Otherwise the LAN91C94 operates in 16 bit mode. NAME TYPE ...
Page 33
... X X two eight bit registers, in that case the offset of each one is independently specified. Regardless of the functional description, when the LAN91C94 bit mode, all registers can be accessed as words or bytes. The default bit values upon hard reset are highlighted below each register. 33 ...
Page 34
Table 3 - Internal I/O Space Mapping BANK0 BANK1 0 TCR CONFIG 2 EPH STATUS BASE 4 RCR IA0-1 6 COUNTER IA2-3 8 MIR IA4-5 A MCR GENERAL PURPOSE C RESERVED (0) CONTROL E BANK SELECT BANK SELECT BANK2 MMU ...
Page 35
... TYPE READ/WRITE BS2 The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2. The LAN91C94 implements only 4 banks, therefore accesses (BS2=1) are ignored. BS1 and BS0 determine the bank presently in use. BS1 BS0 BANK ...
Page 36
... This bit is set and cleared only by the CPU. TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C94 will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted. ...
Page 37
... TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C94 will transmission before stopping. When stopping due to an error, this bit is automatically cleared. LOOPS AT X EPH Block 1 ENDEC 1 Cable 1 10BASE-T Driver 0 ...
Page 38
I/O SPACE - BANK0 OFFSET 2 EPH STATUS REGISTER This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the ...
Page 39
FORCOL in TCR was set the CPU. When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting TXENA in TCR. TX_DEFR - Transmit Deferred. When set, carrier ...
Page 40
... SOFT_RST - Software activated Reset. Active high. Valid for ISA and PCMCIA. Initiated by writing this bit high and terminated by writing the bit low. LAN91C94 configuration preserved, except for Configuration, Base, IA0- 5, COR, and CSR Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times ...
Page 41
I/O SPACE - BANK0 OFFSET 6 COUNTER REGISTER Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do no wrap around beyond 15. HIGH BYTE ...
Page 42
... I/O SPACE - BANK0 OFFSET 8 MEMORY INFORMATION REGISTER For software compatibility with other LAN9000 parts all memory-related information is represented in 256 x M byte units, where the multiplier M is determined by the MCR upper byte. M equals 1 for the LAN91C94. HIGH BYTE 0 0 LOW BYTE 0 0 FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory ...
Page 43
I/O SPACE - BANK0 OFFSET NAME A MEMORY CONFIGURATION REGISTER HIGH BYTE 0 0 LOW BYTE MEMORY RESERVED FOR TRANSMIT (in bytes x 256 MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU ...
Page 44
... If the link status indicates FAIL, the EPHSR LINK_OK bit will be low, while transmit packets enqueued will be processed by the LAN91C94, transmit data will not be sent out to the cable. INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated ...
Page 45
INTERRUPT INT SEL1 INT SEL0 PIN USED 0 0 INTR0 0 1 INTR1 1 0 INTR2 1 1 INTR3 45 ...
Page 46
... A15 - A13 and These bits are compared in ISA mode against the I/O address on the bus to determine the IOBASE for LAN91C94 registers. The 64k I/O space is fully decoded by the LAN91C94 down location space, therefore the address lines A4, A10, A11 and A12 must be all zeros ...
Page 47
A15 A14 A13 ...
Page 48
I/O SPACE - BANK1 OFFSET 4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a ...
Page 49
... EEPROM, that is normally protected from accidental Store operations. This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C94. 49 SYMBOL GPR 0 0 ...
Page 50
... PWRDN - Active high bit used to enter power down mode. Cleared by a write to any register in the LAN91C94 I/O space or by hardware reset. AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). In that case there is no status word ...
Page 51
... During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C94 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750usec. 51 ...
Page 52
I/O SPACE - BANK2 OFFSET 0 MMU COMMAND REGISTER This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH ...
Page 53
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER. Should not be used for frames pending transmission. Typically used to remove transmitted frames, after reading their completion status. Can be ...
Page 54
I /O SPACE - BANK2 OFFSET 2 PACKET NUMBER REGISTER PACKET NUMBER AT TX AREA written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number I/O BANK ...
Page 55
I/O SPACE - BANK2 OFFSET 4 FIFO PORTS REGISTER This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from ...
Page 56
I/O SPACE - BANK2 OFFSET 6 POINTER REGISTER HIGH AUTO BYTE RCV INCR LOW BYTE 0 0 POINTER REGISTER: The value of this register determines the address to be accessed within the transmit or receive areas. It will ...
Page 57
... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C94 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses ...
Page 58
I/O SPACE - BANK2 OFFSET C INTERRUPT STATUS REGISTER ERCV INT EPH INT OFFSET C INTERRUPT ACKNOWLEDGE ERCV INT OFFSET D INTERRUPT MASK REGISTER ERCV INT EPH INT This register can be read and ...
Page 59
Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The possible sources are: LINK_OK transition. CTR_ROL - Statistics counter roll over. TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. ...
Page 60
FIGURE 11 – INTERRUPT STRUCTURE 60 ...
Page 61
OFFSET 0 THROUGH 7 MULTICAST TABLE LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 I/O SPACE - BANK 3 NAME ...
Page 62
HIGH BYTE 0 0 The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of the CRC of the destination addresses. The three determine the register to be ...
Page 63
I/O SPACE - BANK3 OFFSET 8 MANAGEMENT INTERFACE This register contains status bits and control bits for management of different transceivers modules. Some of the pins are shared with the serial EEPROM interface. Management is software controlled, and does not ...
Page 64
... CHIP - Chip ID. Can be used by software drivers to identify the device used. CHIP ID VALUE REV - Revision ID. Incremented for each revision of a given device. NAME TYPE READ ONLY DEVICE LAN91C90/91C92 LAN91C94 LAN91C95 LAN91C100 64 SYMBOL REV REV ...
Page 65
I/O SPACE - BANK3 OFFSET C EARLY RCV REGISTER HIGH BYTE 0 0 LOW RCV BYTE DISCRD 0 0 RCV DISCRD - Set to discard a packet being received. This bit can be used in conjunction with ERCV THRESHOLD and ...
Page 66
... Headers can be analyzed without reading out the entire packet. The packet can be moved in or out with a block move operation. THEORY OF OPERATION Multiple upper layer support - The LAN91C94 facilitates interfacing to multiple upper layer protocols because processing flexibility. scheme like ODI or NDIS drivers is supported ...
Page 67
TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit ...
Page 68
TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 ENABLE RECEPTION - By setting the RXEN bit SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet ...
Page 69
ave Bank Sel ect & Addre ss Ptr R egisters Mas k 91C94 Interrupts Read Interrup t Regist er Yes C all TX INTR or TXEMPT ext TX Pac ket ...
Page 70
RX INTR Wr ite Ad & Read Word 0 f rom RAM Des tination Mult ica st Words from RAM for Addr es s ...
Page 71
TX INTR Save Pkt Number Regist er R ead TXDONE Pkt # f rom Ports Reg. Writ e I nto Packet Number Regist er Write Addr es s Pointer Regist er Read Status Word from RAM Yes ...
Page 72
TXEMPTY I NTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 0 TXEMPTY = X & & TXINT = 0 TXINT = 1 (Waiting for Compl etion) (Transmission Failed) Read Pkt . # Regis ...
Page 73
D RIVER SEND Bank Select R egist er 2 Call ALLOCAT E R ead Int er rupt Status R egister Exit Driver Send Yes Read Allocat ion Result R egister Write Allocated Packet int o Packet # ...
Page 74
... Note that with the memory management built into the LAN91C94, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...
Page 75
... Register. restoring the PNR is also required from interrupt service routines. POWER DOWN This The LAN91C94 can enter power down mode by The means of the PWRDWN pin (pin 68) or the PWRDN bit (Control Register, bit 13). power down current is 8 mA. When in power down mode, the LAN91C94 will: ...
Page 76
... PIN PWRDN PIN PWRDN BIT 0 Normal external ENDEC operation 0 Normal internal ENDEC operation 0 Powerdown - Normal mode restored by PWRDWN pin going low 1 Powerdown - Bit is cleared by a write access to any LAN91C94 register or by hardware reset 76 ...
Page 77
FIGURE 17 – INTERRUPT GENERATION FOR TRANSMIT, RECEIVE and MMU 77 ...
Page 78
FUNCTIONAL DESCRIPTION OF THE BLOCKS MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and de- allocation, it interfaces the arbiter only. The ...
Page 79
... BASE ADDRESS REGISTER, requiring that AEN be low. If the above address comparison is satisfied and the LAN91C94 bit mode, nIOCS16 will be asserted (low). A valid comparison does not yet indicate a valid I/O cycle is in progress, as the addresses could be used for a memory cycle, or could even glitch through a valid value ...
Page 80
... For example ISA system the cycle time bit transfer will be at least 2 clocks for the I/O access to the LAN91C94 + one clock for the memory cycle clocks. In absolute time it means 375ns for a 8MHz bus, and 240ns for a 12.5 MHz bus. The cycle time will not increase when configured ...
Page 81
... The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of packets the LAN91C94 can handle (18). The guideline is software transparency; the software driver should not be aware of different devices or FIFO depths ...
Page 82
FIGURE 18 – MMU PACKET NUMBER FLOW AND REVELANT REGISTERS 82 ...
Page 83
... CSMA/CD block. A packet will be received if the destination address is broadcast addressed to the individual address of the LAN91C94 multicast address and ALMUL bit is set multicast address matching one of the multicast table entries. If the PRMS bit is set, all packets are received. ...
Page 84
... Link_loss_timer Link_test_min_timer Link_count Link_test_max_timer The state of the link is reflected in the EPHSR. AUI The LAN91C94 also provides a standard 6 wire AUI interface to a coax transceiver. PHYSICAL INTERFACE The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T transceiver. ...
Page 85
Transmit Functions Manchester Encoding The PHY encodes the transmit data received from the MAC. The encoded data is directed internally to the selected output driver for transmission over the twisted-pair network or the AUI cable. Data transmission and encoding is ...
Page 86
Reverse Polarity Function In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. Collision Detection Function In the 10BASE-T mode, a collision state is indicated when there are ...
Page 87
... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C94. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, ...
Page 88
... When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C94 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. ...
Page 89
IOS2-0 WORD A DDRESS 10h 11h 10 1 14h 15h 11 0 18h 19h XXX 20h 21h 22h FIGURE 19 – 64 ...
Page 90
For example odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately a full word is completing three bytes into the FIFO. If the CPU reads a word, one byte will be left ...
Page 91
OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range .......................................................................................... 0°C to 70°C Storage Temperature Range ...................................................................................... -55°C to +150°C Lead Temperature Range (soldering, 10 seconds) ................................................................... +325°C Positive Voltage on any pin, with respect to Ground ............................................................ V Negative Voltage ...
Page 92
PARAMETER SYMBOL Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage IP Type Buffers Input Current ID Type Buffers Input Current I/O4 Type Buffer Low Output Level High Output Level V Output ...
Page 93
PARAMETER SYMBOL OD16 Type Buffer Low Output Level Output Leakage OD162 Type Buffer Low Output Level High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby CAPACITANCE T = 25°C; fc ...
Page 94
PARAMETER Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output Voltage (R=78 ...
Page 95
A0 valid REG CE1 t5 7 nWE nOE D0- 7 valid Parameter t57 Write Data Setup to nWE Rising t58 Wri te Data Hold after nWE Rising t59 ...
Page 96
A0-15 AEN, nSBHE VALID ADDRESS t15 nIOCS16 t3 nIORD t5 VALID DAT A D0-15 Parameter t3 Address, nSBHE, AEN Setup to Control Acti ve t4 Address, nSBHE, AEN Hol d after Control Inacti ve t5 nIORD Low to Valid Data ...
Page 97
A0-9,A15 valid t48 nREG t49 nCE1,nCE2 nIORD t47 D0-15 va lid t46 nINPACK Parameter t46 nIO RD Del ay to INPACK t47 nREG Low to Control A ctive t48 nCE1, nCE2 Setup to Control A ct ive t20 Cycle ...
Page 98
A0-15 AEN, nSBHE VALID ADDRESS t15 nIOCS16 t3 nIOWR t7 VALID DATA IN D0-15 Parameter t3 Address, nSBHE, AEN Setup to Control Acti ve t4 Address, nSBHE, AEN Hol d after Control Inacti ve t7 Data Setup to nIOWR Rising ...
Page 99
A0-9, A15 valid t 47 nREG t 48 nCE1, nCE2 t 54 nIOWR valid Parameter t47 nREG Low Setup to Control Active nCE1, nCE2 Setup to Control Active t48 nREG Hol d aft er Control ...
Page 100
A0-15 AEN, VALID ADDRESS nSBHE nIOCS16 nIORD nIOWR IOCHRDY Z D0-D15 VALI D DATA Paramete Control Active to IOCHRDY Low t10 IOCHRDY Low Pulse Width* t20 Cycle ti me** * Note: Assuming ...
Page 101
A 0-15 (ISA ) AEN , nSB HE nIOCS16 nIORD Z IOC HRDY D0-D15 Parameter t 9 Cont rol Active to IOCHRDY Low t18 IOC HRDY Widt h when Data is Unav ai lable at Data Register t19 Valid Data ...
Page 102
A0-15 (ISA) VALID ADDRESS AEN, nSBHE nIOCS16 nIOWR t9 Z IOCHRDY D0-D15 Parameter t9 Control Active to IO CHRDY Low t18 IOCHRDY Width when Data Register is Full IOCHRDY i s used instead of meeting t20 and t44. 'No Wait ...
Page 103
A0-15 VALID ADDRE SS (IS A) AEN nIOWR t3 nIORD t5 Z VALID DATA OUT D0-7 Parameter t3 Address, nSBHE , AEN Setup to Control Acti ve t5 nIORD Low to Valid Data t7 Data Setup to nIOWR Rising t8 ...
Page 104
AEN A0-15, VALID nSBHE t1 BALE t15 nIOCS16 t3 nIO RD nIO WR Parameter t1 Address, nSBHE Setup to BALE Falling t2 Address, nSBHE Hold after BALE Falling t3 Address, nSBHE, AEN Setup to Control A ctive t4 AEN Hold ...
Page 105
A0-19 VALID t1 t2 BALE t3 nMEMRD nRO M Parameter t1 Address Setup to BALE Fal ling t2 Address Hold after BALE F al ling t3 Address Setup to Control Active t16 nMEMRD Low to nROM Low t17 nMEMRD High ...
Page 106
E ESK E EDO E EDI EECS t21 Parameter t21 EE SK Fal ling to EEDO, EECS Changing 9346 i s typically the serial E EPRO M used. FIGURE 32 - EEPROM READ t21 m in typ max 0 100 ...
Page 107
EESK EEDO EEDI EECS t21 Pa rameter t21 EESK Falling to EEDO, E ECS Changing 9346 is typically the serial EEPROM used. FIGURE 33 - EEPROM WRITE mi n typ max 100 107 t21 units ns ...
Page 108
A0-9,A15 valid t67 t67 t67 nFCS nWE t66 nFWE n OE Parameter t66 nWE to nFWE Del ay t67 Address, nREG, nCE1 Delay to nFCS FIGURE 34 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0) va lid t67 ...
Page 109
TXD TXCLK t22 t22 Parameter t22 T XD, nT XEN Delay from TXCLK Fall ing FIGURE 35 – EXTERNAL ENDEC INTERFACE – START OF TRANSMIT t23 RXD RXCLK nCRS t23 Parameter t23 nCRS, RXD Setup to RXCLK Falling t24 ...
Page 110
TPETXP t31 TPETXN t32 TPETXDN t33 TPET XDP TXP t34 TXN Param eter t31 TPETXP to T PETXN Skew t32 TPETXP(N) to TPETXDP(N) Delay t33 TPET XDN to TPETXDP Skew t34 TXP to TXN Skew FIGURE 37 - DIFFERENTIAL OUTPUT ...
Page 111
RECP RECN t35 nCRS (internal) t36 TPERXP(N) t37 nCRS (internal) t38 Parameter t35 Noise Pulse Width Reject (AUI) t36 Carri er Sense Turn On Del ay (AUI) t37 Noise Sense Pul se Width Reject ...
Page 112
T PERXP TPERXN RECP RECN nCRS (internal) Parameter t39 Receiver Turn Off Delay FIGURE 39 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T) t39 min typ max 200 300 112 units ns ...
Page 113
TPETX TXN b TXP TXN Parameter t40 Transmit Output Idle in Half-Step Mode t41 T ransmit Output High before Idle in Hal f-Step Mode FIGURE 40 - TRANSMIT TIMING - END OF FRAME (AUI ...
Page 114
COLLP COLLN t42 COL (internal) Parameter t42 Collision Turn On Delay t43 Collision Turn Off Delay FIGURE 41 - COLLISION TIMING (AUI) t43 min typ max 50 350 114 uni ...
Page 115
POINTER ADDRESS REGISTER nIOWR nIO RD IOCHRDY/ nWAIT (Z) Parameter t44 Pointer Register Reloaded to a Word of Data Prefet ched into Data Register Not e: If t44 is not met, IOCHRDY wil l be negated for the required time. ...
Page 116
0. Millimete rs Inches D IM MIN MAX MIN A 2. 2.57 2. 23. 4 24.15 ...
Page 117
E E1 D1/4 E1 -C- DIM MIN ...
Page 118
-C- MIN NOM 15 13 15. 90 16. ...
Page 119
... LAN91C94 ERRATA SHEET PAGE SECTION/FIGURE/ENTRY 1 Software Drivers and following text 4 General Description 4 Overview 13 Pin Number/TQFP 35 EPH_LOOP 116 100 Pin TQFP/Refer to Table 55 "ETEN" bit 90 MAXIMUM GUARANTEED RATINGS/Operating Temperature Range 90 DC ELECTRICAL CHARACTERISTICS 118 Figure 46 – 100 Pin VTQFP Package Outline *Note: After exiting the loopback test, SRESET in Card Option Register or SOFT_RST in RCR must be set before returning to normal operation ...
Page 120
... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. LAN91C94 Rev. 9/26/97 ...