LAN91C111 SMSC Corporation, LAN91C111 Datasheet
LAN91C111
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LAN91C111 Summary of contents
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... Supports Multiple Embedded Processor Host ■ Interfaces — ARM — SH — Power PC — Coldfire — 680X0, 683XX — MIPS R3000 SMSC LAN91C111-REV B LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY 3.3V MII (Media Independent Interface) MAC-PHY ■ Interface Running at Nibble Rate MII Management Serial Interface ■ ...
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... LAN91C111-NC, LAN91C111i-NC (INDUSTRIAL TEMPERATURE) LAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE) FOR 128 PIN QFP PACKAGES (GREEN, LEAD-FREE) LAN91C111-NE (1.0MM HEIGHT); LAN91C111i-NE (INDUSTRIAL TEMPERATURE) LAN91C111-NU (1.0MM HEIGHT); LAN91C111i-NU (INDUSTRIAL TEMPERATURE) FOR 128 PIN TQFP PACKAGES (GREEN, LEAD-FREE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0.1 Datasheet Revision History Table 0.1 LAN91C111 Datasheet Revision History REVISION LEVEL AND NAME DATE K. Lawrence Rev. 1.8 (07-13-05) Rev. 1.7 (11-16-04) Rev. 1.6 (05-18-04) Rev. 1.6 (05-18-04) Rev. 1.6 (05-18-04) Rev. 1.5 (02-20-04) Rev. 1.5 (02-20-04) Rev. 1.4 (12-12-03) Rev. 1.3 (07-29-03) Rev. 1.3 (07-18-03) Rev. 1.3 (07-18-03) Rev. 1.3 (07-18-03) Rev. 1.2 (09-17-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) SMSC LAN91C111-REV B SECTION/FIGURE/ENTRY Chapter 14, " ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 0.1 LAN91C111 Datasheet Revision History (continued) REVISION LEVEL AND NAME DATE Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) Rev. 1.0 (07-01-02) SMSC LAN91C111-REV B SECTION/FIGURE/ENTRY Section 8.5, "Bank 0 - Add Description for FDUPLX bit. Transmit Control Register," on page 57 Section 8.10, " ...
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... Twisted Pair Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7.9 Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.7.10 Start of Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.7.11 End of Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.7.12 Link Integrity & Autonegotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.7.13 Jabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.7.14 Receive Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.7.15 Full Duplex Mode 7.7.16 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.7.17 PHY Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.7.18 PHY Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 8 MAC Data Structures and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.1 Frame Format In Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2 Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SMSC LAN91C111-REV B 5 DATASHEET Revision 1.8 (07-13-05) ...
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... Chapter 12 Application Considerations 111 Chapter 13 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.1 Maximum Guaranteed Ratings 119 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.3 Twisted Pair Characteristics, Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4 Twisted Pair Characteristics, Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 14 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 6 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SMSC LAN91C111-REV B 7 DATASHEET Revision 1.8 (07-13-05) ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 8 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3.1 Basic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram Figure 7.1 MI Serial Port Frame Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 7.2 MII Frame Format & ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 10 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Tables Table 0.1 LAN91C111 Datasheet Revision History Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package Table 7.1 4B/5B Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7.2 Transmit Level Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8.1 Internal I/O Space Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 9.1 MII Serial Frame Structure Table 9 ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 12 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... Internal output wave shaping circuitry and on-chip filters eliminate the need for external filters normally required in 100Base-TX and 10Base-T applications. The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for embedded application desiring Ethernet connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 14 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... AGND 19 nLNK 20 LBK 21 nLEDA 22 nLEDB 23 GND 24 MDI 25 MDO 26 MCLK 27 nCNTRL 28 INTR0 29 RESET 30 nRD 31 nWR 32 Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP SMSC LAN91C111-REV B Pin Configuration LAN91C111- TM FEAST 128 PIN TQFP 15 DATASHEET 96 nBE2 95 nBE1 94 nBE0 93 GND 92 A15 91 A14 90 A13 89 A12 88 A11 87 A10 ...
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... MDO 28 MCLK 29 nCNTRL 30 INTR0 31 RESET 32 nRD 33 nWR 34 VDD 35 nDATACS 36 nCYCLE 37 W/nR 38 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Pin Configuration LAN91C111- TM FEAST 128 PIN QFP 16 DATASHEET Datasheet 102 D6 101 D7 100 VDD 99 nBE3 98 nBE2 97 ...
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... Chapter 3 Block Diagrams The diagram shown in functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions. The optional Serial EEPROM is used to store information relating to default IO offset parameters as well as which of the Interrupt line are used by the host ...
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... Generic Embedded. The Host interface bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC and ARM processors. The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10/100 Ethernet Physical layer framer to the internal MAC. ...
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... TX25 CRS100 COL100 RXD[3:0] RX_ER RX_DV RX25 MII MDI SERIAL MCLK Manage MDO -ment MII Power PHY AUTONEG On CONTROLS Reset Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram SMSC LAN91C111-REV B LOGIC 19 DATASHEET Multiplexer nPLED[0- LS[2-0]A Multiplexer ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 20 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) FUNCTION System Address Bus System Data Bus System Control Bus Serial EEPROM LEDs PHY Crystal Oscillator Power Ground Physical Interface (MII) ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 22 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... SMSC LAN91C111-REV B BUFFER SYMBOL DESCRIPTION TYPE A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers. A1-A3 I** Input. Used by LAN91C111 for internal register selection. AEN I** Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. nBE0- I** Input. Used during LAN91C111 register nBE3 ...
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... I with Input. When nDATACS is low, the Data pullup** Path can be accessed regardless of the values of AEN, A1-A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C111 32 bits at a time. 24 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... EEPROM configurations. ENEEP I with Input. Enables (when high or open) pullup** LAN91C111 accesses to the serial EEPROM. Must be grounded if no EEPROM is connected to the LAN91C111. XTAL1 Iclk** An external 25 MHz crystal is connected XTAL2 across these pins TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open ...
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... MCLK O4 MII management clock. RX_ER I with Input. Indicates a code error detected by pulldown PHY. Used by the LAN91C111 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13). nCSOUT O4 Output. Chip Select provided for mapping of PHY functions into LAN91C111 decoded space ...
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... Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol at the beginning of a signal name indicates that active low signal. When ‘n’ is not present before the signal name, it indicates an active high signal. The term “ ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 28 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048 byte units. SMSC LAN91C111-REV B 29 DATASHEET Revision 1.8 (07-13-05) ...
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... The data path connection between the MAC and the internal PHY is provided by the internal MII. The LAN91C111 also supports the EXT_PHY mode for the use of an external PHY, such as HPNA. This mode isolates the internal PHY to allow interface with an external PHY through the MII pins ...
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... Figure 7.1. The final 16 bits of the PHY Ml serial port cycle (or 176 bits if multiple register access is enabled and REGAD[4:0]=11111) come from the specific data register designated by the register address bits REGAD[4:0]. SMSC LAN91C111-REV B Figure Table 9.1 9.1and Figure 7.1 are start bits and need to be written for the serial port ...
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... Figure 7.1 MI Serial Port Frame Timing Diagram Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 32 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.5.4 MII Packet Data Communication with External PHY The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements outlined in IEEE 802.3 and shown in TX_EN = 0 IDLE PREAMBLE ...
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... Internal Physical Layer The LAN91C111 integrates the IEEE 802.3 physical layer (PHY) internally. The EXT PHY bit in the Configuration Register the default configuration to set the internal PHY enabled. The internal PHY address is 00000, the driver must use this address to talk to the internal PHY. The internal PHY is placed in isolation mode at power up and reset ...
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... NRZ format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler, respectively, and outputted to the Ethernet controller. SMSC LAN91C111-REV B ETHERNET MAC FRAME ...
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... The mapping of the 5B nibbles to the 4B code words is specified in IEEE 802.3. The 4B5B decoder on the LAN91C111 takes the 5B code words from the descrambler, converts them into 4B nibbles per Table 2, and sends the 4B nibbles to the controller interface. The 4B5B decoder also strips off the SSD delimiter (a ...
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... In Manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. The Manchester decoder in the LAN91C111 converts the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI pulse ...
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... Scrambler 100 Mbps 100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The LAN91C111 scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends it to the TP transmitter. 10 Mbps A scrambler is not used in 10Mbps mode. ...
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... The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category 3/4/5 100 Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied directly to the TP output pins without any external filters. During the idle period, no output signal is transmitted on the TP outputs (except link pulse). SMSC LAN91C111-REV B 39 DATASHEET Figure 7 ...
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... Non-PCI Ethernet Single Chip MAC + PHY TIME (ns) TIME (NS) INTERNAL MAU 100 110 40 DATASHEET Datasheet 100 VOLTAGE (V) 0 1.0 0.4 0.55 0.45 0 -1.0 0.7 0.6 0 -0.55 -0.55 0 1.0 0.4 0.75 SMSC LAN91C111-REV B ...
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... Transmit Rise and Fall Time Adjust The transmit output rise and fall time can be adjusted with the two transmit rise/fall time adjust bits in the PHY Ml serial port Configuration 1. The adjustment range is -0.25ns to +0.5ns in 0.25ns steps. SMSC LAN91C111-REV B TIME (NS) INTERNAL MAU 111 ...
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... The TP transmitter can be powered down by setting the transmit powerdown bit in the PHY Ml serial port Configuration 1 register. When the transmit powerdown bit is set, the TP transmitter is powered down, the TP transmit outputs are high impedance, and the rest of the LAN91C111 operates normally. 7.7.8 Twisted Pair Receiver ...
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... Mbps mode, (5) start of packet is determined when the receiver goes into the unsquelch state an a CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3 Clause 14. SMSC LAN91C111-REV B a. Short Bit Slope 0 585 mV sin ( ...
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... If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 44 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... IEEE 802.3 Clause 14 and shown in Figure 7.6. The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI pulse is detected, data reception is ended and the MAC is notified of no data/invalid data received. SMSC LAN91C111-REV B 45 DATASHEET Revision 1.8 (07-13-05) ...
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... AutoNegotiation is only specified for 100BASE-TX and 10BASE-T operation. 10BASE-T Link Integrity Algorithm - 10Mbps The LAN91C111 uses the same 10BASE-T link integrity algorithm that is defined in IEEE 802.3 Clause 14. This algorithm uses normal link pulses, referred to as NLP's and transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called Link Pass State) ...
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... IEEE 802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast link pulses and referred to as FLP'S, to pass bits of signaling data back and forth between the LAN91C111 and a remote device. The transmit FLP pulses meet the templated specified in IEEE 802.3 and shown ...
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... IEEE 802.3 Clause 28. Once the negotiation process is completed, the LAN91C111 then configures itself for either 10 or 100 Mbps mode and either Full or Half Duplex modes (depending on the outcome of the negotiation process), and it switches to either the 100BASETX or 10BASE-T link integrity algorithms (depending on which mode was enabled by AutoNegotiation) ...
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... SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally determined to be incorrect, and a reverse polarity bit is set in the PHY Ml serial port Status Output register. The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. Autopolarity Disable The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2 register ...
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... PHY Powerdown The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY Ml serial port Control register. In powerdown mode, the TP outputs are in high impedance state, all functions are disabled except the PHY Ml serial port, and the power consumption is reduced to a minimum. To restore PHY to normal power mode, set the PDN bit in PHY MI Register The PHY is then in isolation mode (MII_DIS bit is set) ...
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... RESET pin is held high. The internal PHY is guaranteed to be ready for normal operation 50 mS after the reset pin was de-asserted or the reset bit is set. Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again. SMSC LAN91C111-REV B 51 DATASHEET ...
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... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 52 DATASHEET Datasheet SMSC LAN91C111-REV B ...
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... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA, the CRC, and the CONTROL BYTE. The CRC is not included if the STRIP_CRC bit is set. The maximum number of bytes in a RAM page is 2048 bytes. SMSC LAN91C111-REV B 2nd Byte STATUS WORD ...
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... CPU, including the source address. The LAN91C111 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C111 treated transparently as data both for transmit and receive operations. ...
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... The offset specifies the address of the even byte (bits 0-7) or the address of the complete word. The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. SMSC LAN91C111-REV B HASH VALUE 5-0 000 000 010 000 ...
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... Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C111. Bank new register Bank to the SMSC LAN91C111 device. This bank has extended registers that allow the extended feature set of the SMSC LAN91C111. ...
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... CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal ...
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... LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY chip in loopback mode. TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C111 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. 8.6 ...
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... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C111’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times) ...
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... ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP bit in the TCR is set. STRIP_CRC - When set, it strips the CRC on received frames result, both the Byte Count and the frame format do not contain the CRC ...
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... SPEED bit in the PHY Register 0 (Control Register) when the ANEG_EN bit in the PHY Register 0 (Control Register) is clear. DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control SMSC LAN91C111-REV B NAME TYPE REGISTER ...
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... Register (MAC DUPLEX MODE CONTROL FOR THE MAC SPEED DPLX SWFDUP Bit Bit Bit Register Register Transmit 0 0 Control (PHY) (PHY) Register (MAC SMSC LAN91C111-REV B ...
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... Half Duplex LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to the LEDA output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected. LS2A LS1A LS0A LED SELECT SIGNAL – LEDA ...
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... TX and RX clock so that the Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible. However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is initiated. ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.12 Bank 1 - Base Address Register OFFSET 2 This register holds the I/O address decode option chosen for the LAN91C111 part of the EEPROM saved setup and is not usually modified during run-time. HIGH A15 A14 BYTE 0 0 LOW ...
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... This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111. Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ...
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... The remaining 14 bits of this register will be invalid. During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 µs. ...
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... RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE WRITE ONLY MMU COMMAND BUSY BIT REGISTER READABLE Reserved Reserved 68 DATASHEET Datasheet SYMBOL MMUCR Reserved Reserved BUSY 0 SMSC LAN91C111-REV B ...
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... TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command. OFFSET ALLOCATION RESULT 3 This register is updated upon an ALLOCATE MEMORY MMU command. SMSC LAN91C111-REV B NAME TYPE PACKET NUMBER REGISTER READ/WRITE ...
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... PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively). Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ALLOCATED PACKET NUMBER 0 0 NAME TYPE READ ONLY RX FIFO PACKET NUMBER FIFO PACKET NUMBER DATASHEET Datasheet SYMBOL FIFO SMSC LAN91C111-REV B ...
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... FIFO is empty before loading a new pointer value. This is a read only bit. Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. 8.20 Bank 2 - Data Register OFFSET 8 THROUGH BH SMSC LAN91C111-REV B NAME TYPE READ/WRITE NOT EMPTY IS A READ ONLY BIT ...
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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C111 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers ...
Page 73
... Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register ENABLE (Link Error Enable ENABLE (Counter Roll Over ENABLE (Transmit Error Enable) EPH INT will only be cleared by the following methods: SMSC LAN91C111-REV B NAME TYPE INTERRUPT MASK REGISTER ...
Page 74
... RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 74 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 75
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111-REV B Figure 8.2 Interrupt Structure 75 DATASHEET Revision 1.8 (07-13-05) ...
Page 76
... MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE DATASHEET Datasheet SYMBOL SMSC LAN91C111-REV B ...
Page 77
... Bank 3 - Revision Register OFFSET A REVISION REGISTER HIGH BYTE 0 0 LOW BYTE 1 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC LAN91C111-REV B NAME TYPE MANAGEMENT INTERFACE READ/WRITE Reserved Reserved Reserved MDOE 1 ...
Page 78
... ERCV INT bit of the INTERRUPT STATUS REGISTER is set. 8.26 Bank 7 - External Registers OFFSET 0 THROUG H 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ...
Page 79
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet CYCLE NCSOUT AEN=0 Driven low. Transparently latched on nADS A3=0 rising edge. A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 High Otherwise High SMSC LAN91C111-REV B LAN91C111 DATA BUS Ignored on writes. Tri-stated on reads. Ignore cycle. Normal LAN91C111 cycle. 79 DATASHEET Revision 1.8 (07-13-05) ...
Page 80
... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 80 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 81
... R/LT bits can also be programmed to assert the interrupt function. Bit Type Definition R: Read Only W: Write Only RW: Read/Write R/LT: Read/Latch on Transition REGISTER ADDRESS 6....15 16 SMSC LAN91C111-REV B R/WSC Read/Write : Self Clearing R/LH: Read/Latch high R/LL: Read/Latch low REGISTER NAME Control Status PHY ID Auto-Negotiation Advertisement Auto-Negotiation Remote End Capability Reserved Configuration 1 ...
Page 82
... Write Cycle PHYAD[4:0] Physical PHYSICAL ADDRESS Device Address Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY REGISTER NAME Configuration 2 Status Output Table 9.1 MII Serial Frame Structure <PHY Addr.> <REG.Addr.> PHYAD[4:0] REGAD[4:0] 82 DATASHEET Datasheet Mask Reserved <Turnaround> <Data> TA[1:0] D[15:0] R SMSC LAN91C111-REV B ...
Page 83
... STA shall drive a one bit for the first bit time of the turnaround and a zero bit for the second bit time of the turnaround. D[15:0].... Data These 16 bits contain data to/from one of the eleven registers selected by register address bits REGAD[4:0]. SMSC LAN91C111-REV B 83 DATASHEET R/W W R/W Any ...
Page 84
... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Table 9.2 MII Serial Port Register MAP 84 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 85
... If neither of the previous is true, setting this bit to ‘1’ resets the ANEG process. This bit is self clearing and the PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG process. SMSC LAN91C111-REV B ANEG_EN PDN ...
Page 86
... ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY returns zero if ANEG is disabled. Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY CAP_TF CAP_TH REM_FLT CAP_ANEG DATASHEET Datasheet Reserved Reserved. Reserved LINK JAB EXREG SMSC LAN91C111-REV B ...
Page 87
... Register 4. Auto-Negotiation Advertisement Register NP ACK TX_HDX 10_FDX 10_HDX This register control the values transmitted by the PHY to the remote partner when advertising its abilities SMSC LAN91C111-REV B DEFAULT VALUE 0000000000010110 111110 000100 - - - - RF Reserved Reserved Reserved Reserved ...
Page 88
... The bit definitions are analogous to the Auto Negotiation Advertisement Register. Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY RF Reserved Reserved Reserved Reserved DATASHEET Datasheet Reserved T4 TX_FDX Reserved Reserved CSMA SMSC LAN91C111-REV B ...
Page 89
... Register 16. Configuration 1- Structure and Bit Definition LNKDIS XMTDIS XMTPDN CABLE RLVL0 TLVL3 LNKDIS: XMTDIS: XMTPDN: RESERVED: BYPSCR: UNSCDS: EQLZR: SMSC LAN91C111-REV B Reserved Reserved TLVL2 TLVL1 Link Disable TP Transmit TP Transmit Powerdown RESERVED Bypass Scrambler/Descr- ambler Select Unscrambled Idle ...
Page 90
... STP (150 Ohm UTP (100 Ohm Receive Squelch Levels Reduced By 4 Normal See Table 7 -0.25nS 10 = +0.0nS 01 = +0.25nS 00 = +0.50nS Reserved Reserved Reserved INTMDIO Reserved Reserved Auto Polarity Correction Function Disabled 0 = Normal 1 = Jabber Disabled 0 = Enabled SMSC LAN91C111-REV B ...
Page 91
... Register 18. Status Output - Structure and Bit Definition INT LNKFAIL LOSSSYNC R R/LT R/ SPDDET DPLXDET Reserved R/LT R/ INT: LNKFAIL: LOSSSYNC: CWRD: SMSC LAN91C111-REV Multiple Register Access Interrupt 1 = Interrupt Scheme Select Signaled With MDIO Pulse During Idle 0 = Interrupt Not Signaled On MDIO Reserved for Factory Use CWRD SSD R/LT R/ ...
Page 92
... Detected 1 = Jabber Detected 0 = Normal 1 = Device in 100Mbps Mode (100BASE-TX Device in 10Mbps Mode (10BASE- Device In Full Duplex 0 = Device In Half Duplex Reserved for Factory Use MESD MRPOL MJAB Reserved Reserved Reserved Mask Interrupt For INT In Register 18 SMSC LAN91C111-REV B ...
Page 93
... MSPDDT: MDPLDT: Reserved: 9.10 Register 20. Reserved - Structure and Bit Definition Reserved Reserved Reserved SMSC LAN91C111-REV B Interrupt Mask Link Fail Detect Interrupt Mask Descrambler Loss of Synchronization Detect Interrupt Mask Codeword Error Interrupt Mask Start Of Stream Error Interrupt Mask End Of Stream Error ...
Page 94
... Reserved Reserved Reserved Reserved:Reserved for Factory Use Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Reserved Reserved DATASHEET Datasheet Reserved Reserved Reserved SMSC LAN91C111-REV B ...
Page 95
... Host should not read or write to the registers with the exception of: Configuration Register Control Register Bank Register SMSC LAN91C111-REV B CONTROLLER FUNCTION Ethernet MAC finishes packet currently being transmitted. The receiver completes receiving the current frame, if any, and then goes idle. Ethernet MAC will no longer receive any packets. RX and TX completion FIFO’ ...
Page 96
... Ethernet MAC can now transmit Ethernet Packets. Ethernet MAC is now able to receive Packets. Ethernet MAC is now restored for normal operation. MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. 96 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 97
... No further CPU intervention is needed until a transmit interrupt is generated SMSC LAN91C111-REV B MAC SIDE Upon transmit completion the first word in memory is written with the status word. The packet number is moved from the TX FIFO into the TX completion FIFO. Interrupt is generated by the TX completion FIFO being not empty ...
Page 98
... Byte count is placed at the second word. If the CRC checks correctly the packet number is written into the RX FIFO. The RX FIFO, being not empty, causes RCV INT (interrupt set. If CRC is incorrect the packet memory is released and no interrupt will occur. 98 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 99
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Call EPH INTR Call MDINT SMSC LAN91C111-REV B ISR Save Bank Select & Address Ptr Registers Mask SMC91C111 Interrupts Read Interrupt Register No Yes TX INTR? No ALLOC INTR? ...
Page 100
... Address Filtering Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get Copy Specs from Upper Layer Okay to No Yes Copy? Copy Data Per Upper Layer Specs Issue "Remove and Release" Command Return to ISR Figure 10.2 RX INTR 100 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 101
... Step 4.2.3 Step 4.2.4: Re-Enable Transmission Step 4.2.5: Return from the routine } 5. Restore the Packet Number Register Write Byte (Saved_PNR, (Bank 2, Offset 2)) SMSC LAN91C111-REV B Write (0x00A0, (Bank2, Offset 0)); Temp = Read (Bank 2, Offset 4) Temp = Temp & 0x003F Write (Temp, (Bank2, Offset 2)) // Option 1: Release the packet Write (0x00A0, (Bank2, Offset 0)) ...
Page 102
... Failed) Read Pkt. # Register & Save Write Address Pointer Register Read Status Word from RAM Update Statistics Issue "Release" Command Acknowledge TXINTR Re-Enable TXENA Restore Packet Number Return to ISR 102 DATASHEET Datasheet TXEMPTY = 1 & TXINT = 0 successfully) Update Variables SMSC LAN91C111-REV B ...
Page 103
... Figure 10.5 Drive Send and Allocate Routines MEMORY PARTITIONING Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation ...
Page 104
... In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C111 and provided back to the CPU as their transmission completes. ...
Page 105
... TX EMPTY TWO INT OPTIONS TX INT ALLOC INT 'NOT EMPTY' TX DONE PACKET NUMBER M.S. BIT ONLY Figure 10.6 Interrupt Generation for Transmit, Receive, MMU SMSC LAN91C111-REV B 'NOT EMPTY' PACKET NUMBER REGISTER 'EMPTY' CPU ADDRESS PACK # OUT 105 DATASHEET RX FIFO PACKET NUMBER RX PACKET NUMBER CSMA ADDRESS ...
Page 106
... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 106 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 107
... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C111. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE) that can always be used regardless of the EEPROM based value being programmed ...
Page 108
... STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. Note EEPROM is connected to the LAN91C111, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted ...
Page 109
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet IOS2-0 WORD ADDRESS 000 001 010 011 100 101 110 XXX Figure 11 Serial EEPROM Map SMSC LAN91C111-REV B 16 BITS 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. ...
Page 110
... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 110 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 111
... EISA 32 bit slave VL Local Bus 32 Bit Systems On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions ...
Page 112
... A1, which is tied low in this application. nLDEV is a totem pole output. nLDEV is active on valid decodes of A15- A4 and AEN=0. UNUSED PINS 112 DATASHEET Datasheet nBE3 1 Low word access 0 High word access 1 Byte 0 access 1 Byte 1 access 1 Byte 2 access 0 Byte 3 access SMSC LAN91C111-REV B ...
Page 113
... Delay 1 LCLK nLRDY nLDEV HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C111 is accessed bit peripheral. The signal connections are listed in the following table: Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors ISA BUS LAN91C111 SIGNAL SIGNAL ...
Page 114
... Not used = tri-state on reads, ignored on writes nLDEV is a totem pole output. Must be buffered using an open collector driver. nLDEV is active on valid decodes of A15-A4 and AEN=0. No upper word access. 114 DATASHEET Datasheet D0-D7 D8-D15 Lower Upper Lower Not used Not used Upper SMSC LAN91C111-REV B ...
Page 115
... EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least 1 ...
Page 116
... Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application. Other combinations of nBE are not supported by the LAN91C111. Software drivers are not anticipated to generate them. nLDEV is a totem pole output. nLDEV is active on valid decodes of LAN91C111 pins A15-A4, and AEN=0 ...
Page 117
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet EISA BUS LA2- LA15 RESET AEN M/nIO D0-D31 IRQn nBE[0:3] LATCH nCMD + nWR gates BCLK nSTART nEX32 SMSC LAN91C111-REV B A2-A15 RESET AEN D0-D31 INTR0 LAN91C111 nBE[0:3] nRD nWR LCLK nADS nLDEV O.C. Figure 12.3 LAN91C111 on EISA BUS 117 DATASHEET Revision 1.8 (07-13-05) ...
Page 118
... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 118 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 119
... Low Input Level V High Input Level V Schmitt Trigger Hysteresis V I Input Buffer CLK Low Input Level V High Input Level V SMSC LAN91C111-REV B 0°C to +85°C for LAN91C111 (-40°C to 85°C for LAN91C111I) -55C° 150°C +325° 0.3V CC -0.3V +5V MIN TYP MAX V 0.8 ILI 2 ...
Page 120
... - µ - µ - µ - µ SMSC LAN91C111-REV B ...
Page 121
... Supply Current Active Powerdown Supply Current I CAPACITANCE T = 25° 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance C CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC LAN91C111-REV B MIN TYP MAX 0 -10 + 100 140 CC ...
Page 122
... Pattern Unscrambled, Measure At 50% Points 100 Mbps, Output Data=scrambled /H/ 100 Mbps 10 Mbps 10 Mbps 10 Mbps, NLP and FLP 10 Mbps. 100 Mbps, UTP with TLVL[3:0]=1000 100 Mbps, STP with TLVL[3:0]=1000 10 Mbps, UTP with TLVL[3:0]=1000 10 Mbps, STP with TLVL[3:0]=1000 SMSC LAN91C111-REV B ...
Page 123
... TP Input Squelch Threshold RUT TP Input Unsquelch Threshold TP Input Open Circuit Voltage R CMR TP Input Common Mode Voltage Range RDR TP Input Differential Voltage Range RIR TP Input Resistance Input Capacitance SMSC LAN91C111-REV B UNIT TYP MAX 1.2 1.16 +/-50 % 10K Ohm 15 pF LIMIT UNIT MIN TYP MAX ...
Page 124
... Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 124 DATASHEET Datasheet SMSC LAN91C111-REV B ...
Page 125
... A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming nADS Tied Low) t3 nRD Low to Valid Data t4 nRD High to Data Invalid t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t6 nRD Strobe Width SMSC LAN91C111-REV B Valid Valid MIN ...
Page 126
... A1-A15, AEN, nBE[3:0] Hold after nADS Rising Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 50ns 100ns 150ns Asynchronous Cycle -- Using nADS t9 valid t8 t3 valid valid 126 DATASHEET Datasheet 200ns 250 t4 t5A MIN TYP MAX UNITS SMSC LAN91C111-REV B ...
Page 127
... High to Data Invalid t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t6A nRD Strobe Width Address, AEN, nBE[3:0] nRD, nWR ARDY Data SMSC LAN91C111-REV B 100ns 150ns Asynchronous Cycle - nADS=0 t3A t6A t5 D0~D31 valid Valid Address t26 t26 t13 ...
Page 128
... Non-PCI Ethernet Single Chip MAC + PHY t18 t14 t20 t20 b t15 128 DATASHEET Datasheet MIN TYP MAX UNITS 100 150 t18 t12A t17A t22A t20 c MIN TYP MAX UNITS SMSC LAN91C111-REV B ...
Page 129
... Hold after LCLK Rising t14 nRDYRTN Setup to LCLK Falling t15 nRDYRTN Hold after LCLK Falling t17 W/nR Setup to LCLK Falling t17A W/nR Hold After LCLK Falling t19 Data Delay from LCLK Rising (Read) SMSC LAN91C111-REV B t12 t14 t19 a b t15 MIN ...
Page 130
... Write Data nSRDY Figure 14.8 Synchronous Write Cycle - nVLBUS=0 Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY t8 t9 Valid t25 MIN TYP 8 5 t10 t9 Valid t8 t16 t11 t21 130 DATASHEET Datasheet MAX UNITS t18 t20 t17A Valid t21 SMSC LAN91C111-REV B ...
Page 131
... Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t21 nSRDY Delay from LCLK Rising Clock Address, AEN, nBE[3:0] nADS W/nR nCYCLE Read Data nSRDY nRDYRTN Figure 14.9 Synchronous Read Cycle - nVLBUS=0 SMSC LAN91C111-REV B MIN t10 t9 Valid t8 ...
Page 132
... Non-PCI Ethernet Single Chip MAC + PHY t27 t27 Figure 14.10 MII Timing 132 DATASHEET Datasheet MIN TYP MAX UNITS t28 t28 t28 t29 t29 MIN TYP MAX UNITS SMSC LAN91C111-REV B ...
Page 133
... LEDn Delay Time t35 LEDn Pulse Width 100Mbps t 30 TPO± IDLE IDLE FXO± 10Mbps t 30 TPO± LEDn TXEN Bit is Set SMSC LAN91C111-REV B LIMIT MIN TYP MAX 60 140 600 ±0.7 ±5.5 250 4500 25 80 105 t 31 ...
Page 134
... LIMIT MIN TYP MAX 200 700 300 200 700 500 1500 200 700 134 DATASHEET Datasheet CONDITIONS 100Mbps 10Mbps 10Mbps Measure TPI± from last zero cross to 0.3V point UNIT CONDITIONS nS 100Mbps nS 10Mbps nS 10Mbps nS 100Mbps nS 10Mbps nS 100Mbps nS 10Mbps nS 100Mbps nS 10Mbps SMSC LAN91C111-REV B ...
Page 135
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPO± I DATA TPI± I LEDn MII 10 Mbps TPO± TPI± LEDn SMSC LAN91C111-REV B DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA t 38 Collision Observed ...
Page 136
... DATA DATA DATA DATA DATA DATA t 39 Collision Observed by Physical Layer Collision Observed by Physical Layer t 34 Figure 14.14 Collision Timing, Transmit 136 DATASHEET Datasheet DATA DATA DATA DATA DATA DATA DATA DATA SMSC LAN91C111-REV B ...
Page 137
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPO± TPO± MII 10 Mbps TPI± TPO± SMSC LAN91C111-REV DATA DATA DATA DATA DATA DATA JAM JAM JAM t 41 Collision Observed ...
Page 138
... Link Pulses 138 DATASHEET Datasheet CONDITIONS link_test_min link_test_max lc_max interval_timer transmit_link_burst_time r flp_test_min_timer flp_test_max_timer data_detect_min_timer data_detect_max_timer nlp_test_min_timer nlp_test_max_timer SMSC LAN91C111-REV B ...
Page 139
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet TPO± TPI± LEDn SMSC LAN91C111-REV a.) Transmit NLP t 46 b.) Receive NLP Figure 14.16 Link Pulse Timing 139 DATASHEET t 47 Revision 1.8 (07-13-05) ...
Page 140
... TPI± LEDn Revision 1.8 (07-13-05) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATA CLK t 51 DATA CLK 62.5 93.75 125 t 54 b.) Receive FLP t 58 c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing 140 DATASHEET Datasheet CLK DATA DATA 156. SMSC LAN91C111-REV B ...
Page 141
... Maximum mold protrusion is 0. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Shoulder widths must conform to JEDEC MS-026 dimension ' minimum of 0.20mm. SMSC LAN91C111-REV B MAX REMARK 1.20 Overall Package Height 0 ...
Page 142
... Y Span Measured from Centerline 2 14.10 Y body Size ~ Lead Frame Thickness 1.03 Lead Foot Length ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.30 Lead Width ~ Lead Shoulder Radius 0.30 Lead Foot Radius 0.0762 Coplanarity (Assemblers) 0.08 Coplanarity (Test House) 142 DATASHEET Datasheet SMSC LAN91C111-REV B ...