LAN83C171 SMSC Corporation, LAN83C171 Datasheet
LAN83C171
Specifications of LAN83C171
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LAN83C171 Summary of contents
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... LAN83C171 - EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller IEEE 802.3 Compatible 10/100 Mbps Fast Ethernet Controller Fully Compliant Glueless PCI Version 2.1 Bus Interface Support Included for CardBus Status Registers PCI Universal 3V/5V Output Drives Preemptive Interrupt Support for Efficient ...
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... Ethernet rates of both 100Mb/s and GENERAL DESCRIPTION 10Mb/s. An MII compliant serial management interface is provided to control external media dependent transceivers. The LAN83C171 is a two channel bus master (one for transmit, one for receive) capable of transferring data at the maximum PCI transfer rate of 132Mbps. The ...
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FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION .................................................................................................................2 PIN CONFIGURATION.......................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS .................................................................................................6 FUNCTIONAL DESCRIPTION..........................................................................................................10 PCI INTERFACE..........................................................................................................................12 TRANSMIT/RECEIVE ARBITRATION FOR PCI BUS .................................................................12 SYSTEM ERRORS ......................................................................................................................12 BIG/LITTLE ENDIAN SUPPORT ..................................................................................................12 POWER DOWN MODE ....................................................................................................................14 DMA OPERATION .......................................................................................................................14 TRANSMIT DMA..............................................................................................................................14 Direct Queuing ...
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CONTROL REGISTERS BITS DESCRIPTION .................................................................................45 PCI CONFIGURATION REGISTERS BITS DESCRIPTION...............................................................64 OPERATIONAL DESCRIPTION .......................................................................................................70 Maximum Guaranteed Ratings .....................................................................................................70 DC Electrical Characteristics ........................................................................................................70 TIMING DIAGRAMS ........................................................................................................................72 80 Arkay Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 273-3123 4 ...
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... VDDC 6 RXD3 7 TXD0 8 TXD1 9 TXD2 10 TXD3 TX_EN 11 12 nPHYRST 13 n694EN 14 VSSC 15 MDC 16 MDIO 17 VDDC 18 n694LNK 19 TEST 20 GPIO1 LAN83C171 21 GPIO2/PHY_INT nINTA 22 23 nRST VDDC 24 25 PCICLK VSSC 26 27 VSSG 28 208 Pin QFP nCLKRUN 29 nGNT 30 VDDIO 31 nREQ 32 AD31 VSSPC 33 34 VDDIO VSSG 35 36 ...
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DESCRIPTION OF PIN FUNCTIONS PQFP PIN NO. NAME 25 PCICLK 23 nRST 32,36,37,39,40,42, AD 43,45,49,59-61, 63-65,67,88,89, 91-94,96,97,108, 109,111,112,114, 115,117,118 46,68,87,99 nCBE 86 PAR 70 nFRAME 71 nIRDY 74 nTRDY 77 nSTOP 79 nLOCK 48 IDSEL 75 nDEVSEL 31 nREQ 29 ...
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PQFP PIN NO. NAME 22 nINTA 54 nPME 28 nCLKRUN EXTERNAL MEMORY INTERFACE 140 MA15/nRAMW R 139-135,133,132, MA 128,127,125-120 183,181-162, MD/JMP 153-143 186 nRAMOE 185 nRAMCS 188 nROMCS 161 nROMWE 187 EECS 190 TX_CLK 11 TX_EN 10-7 TXD 194 RX_CLK ...
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PQFP PIN NO. NAME 196 CRS 6,199-197 RXD 195 COL 193 RX_DV 192 RX_ER 15 MDC 16 MDIO 18 n694LNK 13 n694EN 4 SYSCLK 20 GPIO1 21 GPIO2/PHY_INT 19 TEST 204 X20 202 BIAS 201 ZENER 12 nPHYRST 5,17,24,81,110,131 VDDC ...
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PQFP PIN NO. NAME 2,129,141,154,182 VDDAC 34,50,72,101,30, VDDIO 38,52,55,85,95, 103,105,116,57,66, 107 200 VDDA 1,14,26,73,98,126, VSSC 134,159,189,206, 207 3,130,142,155,160, VSSAC 184 27,35,78,100 VSSG 33,41,47,51,53,56, VSSPC 62,69,76,82,90, 102,104,106,113 44,80,119 VSSIO 58,203 VSSA I/O TYPE DESCRIPTION PWR Connect to +5V PWR Connect to ...
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... The LAN83C171 is a two channel bus master (one for transmit, one for receive) capable of transferring data at the maximum PCI transfer rate of 132 Mbps. Buffer format in host memory is controlled by an independent linked list structure for each channel ...
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... PCI LOCAL BUS PCI RECEIVE DMA 4.5 KBytes PCI BUS MASTER REGISTERS / SLAVE INTERFACE PCI TRANSMIT DMA 1.5 KBytes CLOCK MULT. SYS CLOCK FIGURE 1 - LAN83C171 BLOCK DIAGRAM EXTERNAL BOOT ROM RECEIVE (OPTIONAL) BUFFER (OPTIONAL) INTERNAL RECEIVE CSMA/CD RECEIVE MTU TRANSMIT BUFFER MII MANAGEMENT CSMA/CD ...
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... In order to comply with the PCI specification, the LAN83C171 does not swap the data bytes on reads or writes to the configuration or control register space. responsible for interpreting correctly the bytes when performing 32 bit register read or writes on a Big Endian machine ...
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Control Register dword transfer Descriptor/Fragment list dword transfer FIGURE 2 - LITTLE ENDIAN/BIG ENDIAN BYTE TRANSFER The number in the ...
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... The host may power down the LAN83C171 by writing the power down bit in the general control register. When the bit is set, the chip's internal system clock is gated off to reduce switching current (the ...
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... LAN83C171 will clear TXQUEUED and set the transmit queue empty interrupt. If the ownership bit is 1, the LAN83C171 will begin copying the next frame into the local transmit RAM. The DMA will continue copying transmit buffers until the frame has been completely loaded into the transmit RAM or the first transmission has completed ...
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... LAN83C171 will post the status into the first descriptor and immediately initiate the second transmission. If the transmission completes before the copy is done, the LAN83C171 will pause between fragments to post the status and then resume the copy. If the early transmit threshold has already been exceeded then the second transmission will be initiated immediately ...
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FRAME 1 STATUS TX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS TX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS FRAME 2 STATUS TX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS FRAGLIST = 1 FIGURE 3 - TRANSMIT ...
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... TXQUEUED can be written regardless of completion status and will ensure that the latest frame is transmitted. If the LAN83C171 reaches the end of the transmit queue before the new frame has been added, a transmit chain complete interrupt is generated for the old portion of the queue and another transmit chain complete interrupt will be generated when the added portion completes ...
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... The The fragment list format for the receive DMA is identical to the format for the transmit DMA. As soon as a frame is received, the LAN83C171 will begin copying it from the local buffer into the allocated buffer in host memory. The first ...
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... The RXQUEUED bit may be set at any time, even if the receive DMA is still active. Receive Lookahead Method When this buffering method is used, the LAN83C171 first copies only the header of a frame into host memory, and then waits for a to queue from the software driver before copying the rest of the frame ...
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... However, the next descriptor in the receive descriptor list must have the ownership bit cleared (host still owns descriptor). This allows the LAN83C171 to update the PRSTAT register without starting to copy the following frame. The software driver must poll the RQE (receive queue empty) interrupt to determine when the status is available ...
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When the software driver wants only one more copy of the current frame, it does not have to wait for the copy to complete before setting NEXTFRAME. ...
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Figure 4 shows an example of the Receive RX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS RX LENGTH/STATUS FRAGLIST ADDRESS CONTROL/OFFSET NEXT DESCR. ADDRESS FRAGLIST = 1 RX LENGTH/STATUS FRAGLIST ADDRESS FRAME 1 STATUS/LENGTH CONTROL/OFFSET NEXT DESCR. ADDRESS FRAGLIST ...
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READ DESCRIPTOR GO TO NEXT FRAME COPY HEADER POST STATUS TRUE NEXTFRAME READ DESCRIPTOR COPY FRAME POST STATUS RDMA STOPPED (RXQUEUED=0) FALSE NEXTFRAME FIGURE 5 - RECEIVE LOCKAHEAD BUFFERING FLOW RESET WAIT RXQUEUED SET HEADER BIT SET OWNER HOST/CLEAR RXQUEUED ...
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... A lower threshold allows the LAN83C171 to begin moving data on the PCI bus sooner, while a higher threshold may allow longer bursts. A higher threshold level will not result in longer data bursts if the receive FIFO never reaches the empty level (due to latencies on the PCI bus) ...
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... MAC OPERATION The LAN83C171 is compliant with the 802.3 standard CSMA/CD protocol for 10 or 100Mb/s Ethernet networks. MAC TRANSMITTER The LAN83C171 CSMA/CD transmitter capable of generating network data at rates of 10 and 100Mb/s. It supports implementations of 10Mb/s physical devices, and the 802.3u Media Independent Interface (MII) for 10 and 100Mb/s. ...
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Interframe Gap and Deference Deference is initiated when both CRS and COL have terminated at the end of a packet. The transmitter deference logic initiates a 2-part timer at the end of network activity. While this timer is running, no ...
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... COL signals provide carrier sense and collision detect respectively. In parallel mode, the physical layer device transfers data to the LAN83C171 four bits at a time on the RXD[3-0] data bus. transferred synchronously to the falling edge of RXC. The signal Receive Data Valid (RX_DV) informs the MAC of the RXD bus status. The ...
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Error Detection The receiver computes the CRC of incoming frames for all data following the detection of SFD in both parallel and serial mode until the end of frame, including the CRC field. Computation stops after the reception of the ...
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The return of acknowledge is guaranteed to prevent the receive FIFO from overflowing. The data path to the receive local memory is 32 bits. If the receive local memory becomes full during ...
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... PHY register once. Writing an entire PHY register option permits lower PCI bus utilization. The LAN83C171 serializes this data and writes it to the PHY via MDC and MDIO. EEPROM INTERFACE The LAN83C171 has a serial interface to external EEPROM ...
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... JUMPER OPTIONS (EEPROM/RAM) There are several operational modes in the LAN83C171 which are selected by "jumpers" at power-up reset. Actual jumpers do not need to be installed on the board. The options can be set by external pull-up or pull-down resistors at manufacturing time. Pins MD[4:0] are used to make the jumper selections. ...
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PMCSR. The PME status and enable bits in the PMCSR will not be altered by the assertion of PCI reset. The bits will, however, be cleared at initial power-up by the EPIC as described below. Therefore, the EPIC will maintain ...
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MODE v D3(Cold1) Auxiliary powered mode (no PCI sourced power) Same as D3(Hot) with the following exception. As the PCI Bus clock will be disabled, access to the EPIC Configuration Address space will not be possible vi D3(Cold2) No power ...
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Before placing the EPIC into one of the low power states, the driver shall ensure that there are no ongoing network receptions transmissions in progress involving the EPIC (i.e. the EPIC idle state). Otherwise, the corruption of ...
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Special Power Management Mode A special mode can be enabled to have the EPIC transition to power state D3(Cold1) upon the loss of PCI Bus sourced power to the EPIC. a) This special mode can be enabled by setting bit ...
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... DMA controllers could corrupt host memory with a bus master operation that was started before the warm boot. When the soft reset bit is set, the LAN83C171 takes 15 PCI clocks to re- initialize itself. The device must not be accessed within that time period. ...
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... The write pulse for each individual byte write will be 200 ns. EPIC/100 will write all bytes in a dword that have valid byte enables during the data phase access is made to the LAN83C171 while a flash write is physically taking place, a retry will be issued on the PCI bus. MEMORY ...
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DMA DESCRIPTOR BITS DESCRIPTION TRANSMIT DMA DESCRIPTOR BITS DESCRIPTION The following diagram shows the format of the transmit descriptor table LENGTH BUFFER ADDRESS CONTROL NEXT DESCRIPTOR ADDRESS DWORD 0 - STATUS/LENGTH Bit Number Description 31 through 16: Transmit ...
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NON-DEFERRED TRANSMISSION: This bit is set if the frame is transmitted successfully without deferring. transmission can only occur the first time an attempt is made to send a packet. Collisions are not deferred transmissions PACKET TRANSMITTED: ...
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RECEIVE DMA DESCRIPTOR BITS DESCRIPTION The following diagram shows the format of the 31 RX LENGTH BUFFER ADDRESS CONTROL NEXT DESCRIPTOR ADDRESS DWORD 0 - LENGTH/STATUS Bit Number Description 31 through 16 - RECEIVE FRAME LENGTH: Number of bytes in ...
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PACKET RECEIVED INTACT: This bit is set when a packet is received into the buffer space without error. DWORD 1 - DATA BUFFER/START OF FRAGLIST POINTER Bit Number Description 31 through 0 - Starting address of data buffer ...
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... Legal to access during transmit underrun only. 3 Legal to access only when frame is discarded after header copy and INTSTAT.RSV Legal to access only in test mode. The following table shows the address mapping of the LAN83C171 control registers. All registers are dword accessible only LAN0 80 ...
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... CONFIGURATION REGISTERS MAP The following table shows the address mapping for the LAN83C171 configuration registers Device ID 04 Status 08 0C Unused Subsystem Max Lat Power Management(PM) Capabilities E0 Unused Note: All unused and reserved registers return zeroes, when read. Writes to unused and reserved registers are ignored ...
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... NEXTFRAME: This bit is set by the host to indicate that it does not need any more copies of the current receive frame. The bit will be cleared by the LAN83C171 the next time it reads a descriptor. Writing this bit has no effect (in register test mode writing 0 clears the bit RXQUEUED: This bit is set to queue a receive descriptor ...
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RCTS: Receive copy threshold status (read only - does not generate an interrupt) - indicates that the copy in progress that has passed the early receive copy threshold. This bit returns zero when there is no receive copy ...
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TXC: Transmit complete - set when a packet has been successfully transmitted or aborted and the IAF bit is set for that frame RXE: Receive error - set when a CRC error occurs and Monitor mode ...
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PME INTA ENABLE: This bit enables the occurrence of an enabled PME during one of the low power states to set bit 14 of the Interrupt Status register MAGIC PACKET ENABLE: enables the detection of a ...
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... INTSTAT(15), and is normally used as an interrupt indication from the physical layer GENERAL PURPOSE OUTPUT ENABLE[1]: When set, GPIO[1] is driven by the LAN83C171. When cleared, GPIO[1] is tri-stated and may be used as an input CLOCK RUN SUPPORTED: enables the LAN83C171 to perform the PCI clock run function ...
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... The value of this bit is muxed onto MA[14] when EEPROM ENABLE is set EECS: EEPROM chip select - This bit is wired directly to the EECS output pin on the LAN83C171 EEPROM ENABLE: When this bit is set, EESK and EEDI are multiplexed onto the MA pins. 18 – PBLCNT Register ...
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Reports the number of missed packet errors since the last time this register was read. The count will stay at 255 when reached the max. When the count reaches 192, the counter overflow interrupt will be set. ...
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... LAN83C171 ENABLE 694: When set, the EN694 pin of the LAN83C171 is driven to a logic one. When clear, the EN694 pin is driven low SERIAL MODE ENABLE: When set, the MII interface functions serially as a 7-wire interface. ...
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LAN0 [3- LAN1 [15-12 LAN1 [11- LAN1 [7- LAN1 [3- LAN2 [15-12] = N11 LAN2 [11-8] = N10 LAN2 [7- LAN2 [3- BOARD ID/CHECKSUM ...
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RECEIVE STATUS Reset Value: 0000000 The receive status register reports the status of the most-recently received packet. receive errors and address recognition type. All bits are cleared at the start of reception except for receiver disabled. The contents ...
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LOOPBACK MODE SELECT Mode 0 0 Normal operation Internal loopback. Packets transmitted are internally looped back to the receiver without transmission to the MII External loopback. Turns on the external ...
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Reads to this register return unknown data. 31 through 9 - Unused. 8 through 0 - Address TRANSMIT TEST 31 through 12 - Unused. 11 through 8 - Reserved: Do ...
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ADDRESS. 1 and 0 - Not writable - always return zeroes PCI RECEIVE DMA DATA LENGTH / CONTROL BITS Reset Value: xxxxxxxxxxxxxxxxxxxx This register contains the number of bytes remaining in the current data ...
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A0 - PCI RECEIVE END OF FRAME ADDRESS Reset Value: xxxxxxxxxxxxxxxxxx This register contains the byte address of the DWORD location immediately following the end of the current frame in the local receive RAM. The two LSBs contain the number ...
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... B0 - PCI RECEIVE COPY THRESHOLD Register Reset Value: 11111111XX This register is programmed with the PCI receive copy threshold for the LAN83C171. An early receive warning interrupt will be generated for each frame after the number of bytes, specified in this register, have been copied into the receive data buffers in the host memory. ...
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PCI ADDRESS. 1 and 0 - Not writable - always return zeroes PCI TRANSMIT CURRENT DESCRIPTOR ADDRESS Register Reset Value: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00 This register contains the byte address (in host memory) of the next descriptor ...
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... When this register is written by the host, it will be loaded with the current value in the TXSTAT register. Reads work normally. The transmit length register and transmit length LAN83C171. counter are also writable through the upper word at this address. 31 through 16 - TRANSMIT LENGTH: ...
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OWNER: Descriptor ownership bit - This bit is writable at this location, but may only be read at bit 21 in the PTDLGTH register. When read here, this bit always returns a ‘0’ to set the descriptor ownership ...
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FO – FEVTR Register Reset Value: 0XXXXXXXXXXXXXXX This bit is used for CardBus purposes. CardBus mode must be set in the NVCTL register bit 6 for this function to be available FEVTR: This function event register bit is ...
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... LAN83C171 always asserts DEVSEL with fast timing (zero wait states DATA PARITY DETECTED: This bit is set whenever the following three conditions are met: 1) the LAN83C171 is acting as bus master on the PCI bus; 2) the LAN83C171 asserts nPERR or observes nPERR asserted; 3) the Parity Error Response bit is set ...
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... HEADER TYPE/LATENCY Register 31 THROUGH 24: Unused (returns 00h MULTI-FUNCTION DEVICE: returns 0 to indicate that the LAN83C171 is a single function PCI device. 22 through 16 - HEADER TYPE: Specifies the format of bytes 10h - 3Ch in the configuration space (00h). 15 through 8 - LATENCY TIMER: This byte is programmed with the value of the Latency Timer (in PCI bus clocks) for LAN83C171 bus master operations ...
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... LAN83C171 needs to gain access to the PCI bus.* To enable performance tuning, the value is recalled from EEPROM after reset. 23 through 16 - MINIMUM GRANT: This read only field specifies the length of a burst period the LAN83C171 needs assuming a 33 MHz PCI 66 Controls LAN83C171 accepts This ...
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... LAN83C171's interrupt pin is connected to. Values in this register are system architecture specific. * The maximum latency and minimum grant registers are used to indicate the LAN83C171's desired settings for Latency Timer values. Both registers specify a period of time in units of 1/4 that the microsecond. For example, if the LAN83C171 ...
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DC – POWER MANAGEMENT REGISTER st BLOCK (1 Half) Reset Value: x1110110001x00010000000000000001 Bits 31 through 16 of this register are collectively known as the “Power Management Capabilities”. This entire register is read only D3(COLD1) PME SUPPORT: indicates whether ...
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PM DATA: These bits will return 00h (read only) since the EPIC does not support the read back of power and heat dissipation information. 23 through 16 - BRIDGE EXTENSIONS: These bits will return 00h (read ...
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OPERATIONAL DESCRIPTION Maximum Guaranteed Ratings Operating Temperature Range......................................................................................... +70 C Storage Temperature Range....................................................................................... - +150 C Lead Temperature Range (soldering, 10 Seconds).................................................................... +325 C Positive Voltage on any pin with respect to Ground .............................................................. V ...
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PARAMETER SYMBOL PCI TTL PCI TTL Low Input Voltage V High Input Voltage Low Input Voltage V High Input Voltage TTL TTL Low ...
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PCICLK t3 nFRAME t3 t3 nCBE FIGURE 6 - PCI COMMAND TIMING MASTER NAME MIN MAX t1 t2 2ns 11ns t3 2ns 11ns TIMING DIAGRAMS TARGET MIN MAX DESCRIPTION 7ns Input setup to clock 0ns (Master) ...
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PCICLK nFRAME nTRDY nDEVSEL FIGURE 7 - PCI/nDEVSEL TIMING MASTER NAME MIN MAX t1 0ns t2 7ns t2 t1 TARGET MIN MAX DESCRIPTION 2ns 11ns (Master) Input hold time from clock (Target) Clock to signal valid delay Input setup to ...
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PCICLK nIRDY nTRDY FIGURE 8 - PCI/nIRDY AND nTRDY TIMING MASTER NAME MIN MAX t1 t2 2ns 11ns t3 7ns t4 0ns t5 2ns 11ns TARGET MIN MAX DESCRIPTION 7ns Input setup time to ...
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PCICLK nFRAME nTRDY AD (Add/Data) FIGURE 9 - PCI/DATA READ TIMING MASTER NAME MIN MAX t1 0ns t2 7ns TARGET MIN MAX DESCRIPTION 2ns 11ns (Master) Input hold time from clock (Target) Clock to signal valid Input ...
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PCICLK nFRAME nTRDY AD (Add/Data) FIGURE 10 - PCI/DATA WRITE TIMING MASTER NAME MIN MAX t1 t2 2ns 11ns t2 t1 TARGET MIN MAX DESCRIPTION 7ns Input setup time to clock 0ns (Master) Clock to signal valid delay (Target) Input ...
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PCICLK IDSEL nFRAME Config Addr AD nCBE Config Write nIRDY nTRDY nSTOP nDEVSEL Addr Par PAR FIGURE 11 - PCI - TYPICAL CONFIGURATION WRITE/EPIC IS TARGET Config Data BE Data Par PCI Bus Cycle Illustration 77 TRG_CFWR.TD ...
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PCICLK IDSEL nFRAME AD Config Addr nCBE Config Read nIRDY nTRDY nSTOP nDEVSEL PAR Addr Par FIGURE 12 - PCI - TYPICAL CONFIGURATION READ/EPIC IS TARGET Config Data BE PCI Bus Cycle Illustration 78 Data Par TRG_CFRD.TD ...
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PCICLK nFRAME AD Address nCBE I/O Read nIRDY nTRDY nSTOP nDEVSEL PAR FIGURE 13 - PCI - TYPICAL I/O READ/EPIC IS TARGET Data BE Addr Par PCI Bus Cycle Illustration 79 Data Par TRG_IORD.TD ...
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PCICLK nFRAME AD Address nCBE I/O Write nIRDY nTRDY nSTOP nDEVSEL PAR Addr Par FIGURE 14 - PCI - TYPICAL I/O WRITE/EPIC IS TARGET Data BE Data Par PCI Bus Cycle Illustration 80 TRG_IOWR.td ...
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PCICLK nREQ nGNT nFRAME AD Address nCBE Read Cmd nIRDY nTRDY nSTOP nDEVSEL PAR FIGURE 15 - PCI - TYPICAL READ TRANSACTION/SYSTEM MEMORY TO CHIP Data 1 Data Data Par 1 Data Par 2 Addr ...
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PCICLK nREQ nGNT nFRAME AD Address nCBE Write Cmd nIRDY nTRDY nSTOP nDEVSEL PAR FIGURE 16 - PCI - TYPICAL WRITE TRANSACTION/CHIP TO SYSTEM MEMORY Data 1 Data Addr Par Data Par 1 Data Par ...
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TX_CLK TXD TX_EN CRS (1/2 Dup) FIGURE 17 - MII - TRANSMIT TIMING FOR 10/100Mb/s Note: Clock Frequency Changes to 2.5 MHz for 10 Mb/s Nibble Transfers NAME MIN t1, t2 0ns t3 0ns(100Mb/s) 0ns(10Mb/s) t4 0ns(100Mb/s) 0ns(10Mb/ ...
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RX_CLK RXD RX_DV CRS (1/2 Dup) FIGURE 18 - MII - RECEIVE TIMING FOR 100Mb/s Note: Clock Frequency Changes to 2.5MHz for 10Mb/s Nibble Transfers NAME MIN t1, t3 10ns t2, t4, t5 10ns MAX DESCRIPTION Input ...
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RX_CLK RXD t4 RX_DV RX_ER RX_ER expected least 1 clk if CRS (1/2 Dup) error, otherwirse 2 clks FIGURE 19 - MII - RECEIVE ERROR (RX_ER) TIMING FOR 100Mb/s Note: Clock Frequency Changes to 2.5 MHz for ...
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W MDC t1 t2 MDIO Write Data WRITE FIGURE 20 - MII - SERIAL MANAGEMENT WRITE/READ NAME MIN t1 10ns t2 10ns t3 0ns R t3 Read Data READ MAX DESCRIPTION Data ready before the rising edge of MCLK (Setup ...
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MA nRAMOE nRAMCS MD/JMP FIGURE 21 - EXTERNAL(OPTIONAL) RAM READ NAME MIN t1 0ns 0ns Address MAX DESCRIPTION Address setup before output enable 250ns Chip select access time 250ns Output enable to data valid ...
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MA nRAMOE nRAMCS MA/15nRAMWR MD/JMP FIGURE 22 - EXTERNAL (OPTIONAL) RAM WRITE NAME MIN t1 210ns t2 120ns t4 110ns t5 180ns t6 200ns t7 120ns t1 t2 Address Data to RAM MAX DESCRIPTION Address ...
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FIGURE 23 - 208 PIN PQFP PACKAGE OUTLINE, 2.6 MM FOOTPRINT See Table on the following page. 89 ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. REMARK LAN83C171 Rev. 08/26/97 ...