GS72116ATP-10 GSI Technology, GS72116ATP-10 Datasheet

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GS72116ATP-10

Manufacturer Part Number
GS72116ATP-10
Description
10ns 128K x 16 2Mb asynchronous SRAM
Manufacturer
GSI Technology
Datasheet

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SOJ, TSOP, FP-BGA, TQFP
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a sin-
gle 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions
Rev: 1.04a 10/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
minimum cycle time
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
DQ
Symbol
A
0
1
V
V
WE
CE
UB
OE
NC
LB
–A
–DQ
DD
SS
16
16
Lower byte enable input
Upper byte enable input
2Mb Asynchronous SRAM
+3.3 V power supply
Output enable input
Write enable input
Chip enable input
Data input/output
Description
(DQ9 to DQ16)
(DQ1 to DQ8)
Address input
No connect
Ground
128K x 16
1/18
SOJ 128K x 16-Pin Configuration
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
V
A
V
WE
A
A
A
A
CE
A
A
A
A
A
DD
12
SS
15
14
13
16
4
3
2
1
0
1
2
3
4
5
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Package J
Top view
44-pin
SOJ
© 2001, Giga Semiconductor, Inc.
Center V
GS72116ATP/J/T/U
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
7, 8, 10, 12 ns
DD
3.3 V V
A
A
A
OE
UB
LB
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
NC
5
6
7
SS
DD
8
9
10
11
and V
16
15
14
13
12
11
10
9
DD
SS

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GS72116ATP-10 Summary of contents

Page 1

... SOJ 128K x 16-Pin Configuration DQ6 DQ7 Address input Ground No connect 1/18 GS72116ATP/J/T 10 Center Top view ...

Page 2

... mm, 0.75 mm Bump Pitch Top View Package U 2/18 GS72116ATP/J/T ...

Page 3

... A14 Package TP Row Memory Array Decoder Address Input Buffer Column Decoder I/O Buffer Control DQ 1 3/18 GS72116ATP/J/T ...

Page 4

... High Z Symbol Rating V –0.5 to +4.6 DD –0 +0 4.6 V max.) –0 +0 OUT ( 4.6 V max.) PD 0.7 T –55 to 150 STG 4/18 GS72116ATP/J/T Current Not Selected ISB , ISB 1 2 Read High Z Read Write I DD Not Write, High Z Write High Z High Z Unit ...

Page 5

... OUT Test Conditions Min – Output High Z – OUT –4mA 2 +4mA — LO 5/18 GS72116ATP/J/T/U Max Unit Unit Max — 0.4 V © 2001, Giga Semiconductor, Inc. ...

Page 6

... Conditions V/ns 1.4 V 1.4 V Fig. 1& 2 6/18 GS72116ATP/J/T/U –40 to 85° 130 mA 105 Output Load 30pF VT = 1.4 V Output Load 2 3.3 V 589 ...

Page 7

... BLZ * — 3.5 — — 3 — t OHZ * — 3 — t BHZ , UB and Previous Data 7/18 GS72116ATP/J/T/U -10 -12 Max Min Max Min Max — 10 — 12 — 8 — 10 — — 10 — 12 3.5 — 4 — 5 3.5 — 4 — 5 — 3 — ...

Page 8

... GS72116ATP/J/T/U tHZ tBHZ tOHZ Data valid -10 -12 Max Min Max Min Max — 10 — 12 — — 7 — 8 — — 7 — 8 — — 7 — 8 — — ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tCW tBW tAS tWP tDW Data valid tWHZ High impedance tWC tAW tAS tCW tBW tWP tDW tDH Data valid High impedance 9/18 GS72116ATP/J/T/U tWR tDH tWLZ tWR1 © 2001, Giga Semiconductor, Inc. ...

Page 10

... Address Data In Data Out Rev: 1.04a 10/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tAS tCW tBW tWP tDW tDH Data valid High impedance 10/18 GS72116ATP/J/T/U tWR1 © 2001, Giga Semiconductor, Inc. ...

Page 11

... Detail Note: 1. Dimension D& not include interlead flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: inches 11/18 GS72116ATP/J/T/U Dimension in inch Dimension in mm min nom max min nom 0.148 — — — — 0.025 — — 0.635 — ...

Page 12

... Detail A Note: 1. Dimension D& not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm 12/18 GS72116ATP/J/T/U Dimension in inch Dimension in mm min nom max min nom 0.047 — — — — 0.002 — — 0.05 — 0.037 ...

Page 13

... 0.1 Units: mm Rev: 1.04a 10/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Body Thickness Lead Length Lead Width A2 L1 1.4 1.0 13/18 GS72116ATP/J/T Lead Thickness Lead Pitch 0.3 0.127 0.8 © 2001, Giga Semiconductor, Inc. ...

Page 14

... Lead Count 0.1 Units: mm Rev: 1.04a 10/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Lead Length Lead Width Lead Thickness Lead Pitch 1.4 1.0 0.3 14/18 GS72116ATP/J/T 0.127 0.8 © 2001, Giga Semiconductor, Inc. ...

Page 15

... Fine Pitch BGA Rev: 1.04a 10/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0.10 ± 8.00 5.25 15/18 GS72116ATP/J/T/U 0.10 © 2001, Giga Semiconductor, Inc. ...

Page 16

... GS72116ATP-7 400 mil TSOP-II GS72116ATP-8 400 mil TSOP-II GS72116ATP-10 400 mil TSOP-II GS72116ATP-12 400 mil TSOP-II GS72116ATP-7I 400 mil TSOP-II GS72116ATP-8I 400 mil TSOP-II GS72116ATP-10I 400 mil TSOP-II GS72116ATP-12I 400 mil TSOP-II GS72116AJ-7 GS72116AJ-8 GS72116AJ-10 GS72116AJ-12 GS72116AJ-7I GS72116AJ-8I GS72116AJ-10I GS72116AJ-12I GS72116AT-7 ...

Page 17

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Package Access Time 17/18 GS72116ATP/J/T/U Temp. Range Status Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial © 2001, Giga Semiconductor, Inc. ...

Page 18

... Updated Recommended Operating Conditions table on page 5 Content • Removed 15 ns bin • Changed FPBGA package from (package U) • Removed 6 ns speed bin from entire document Content • Added 7 ns speed bin to entire document 18/18 GS72116ATP/J/T/U © 2001, Giga Semiconductor, Inc. ...

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