GS88036AT-166 GSI Technology, GS88036AT-166 Datasheet

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GS88036AT-166

Manufacturer Part Number
GS88036AT-166
Description
166MHz 7ns 256K x 36 9Mb synchronous burst SRAM
Manufacturer
GSI Technology
Datasheet

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Part Number:
GS88036AT-166
Manufacturer:
GSI
Quantity:
1
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS88018/32/36AT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Through
Pipeline
3-1-1-1
2-1-1-1
operation
3.3 V
2.5 V
Flow
3.3 V
2.5 V
Curr
Curr
Curr
Curr
Curr
Curr
Curr
Curr
tCycle
tCycle
t
t
(x32/x36)
(x32/x36)
(x32/x36)
(x32/x36)
KQ
KQ
(x18)
(x18)
(x18)
(x18)
-250 -225 -200 -166 -150 -133 Unit
280
330
275
320
175
200
175
200
2.5
4.0
5.5
5.5
255
300
250
295
165
190
165
190
512K x 18, 256K x 32, 256K x 36
2.7
4.4
6.0
6.0
230
270
230
265
160
180
160
180
3.0
5.0
6.5
6.5
9Mb Sync Burst SRAMs
200
230
195
225
150
170
150
170
3.4
6.0
7.0
7.0
185
215
180
210
145
165
145
165
3.8
6.7
7.5
7.5
165
190
165
185
135
150
135
150
4.0
7.5
8.5
8.5
1/26
mA
mA
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
SCD Pipelined Reads
The GS88018/32/36AT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88018/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
GS88018/32/36AT-250/225/200/166/150/133
DDQ
) pins are used to decouple output noise
© 2001, Giga Semiconductor, Inc.
250 MHz–133 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS88036AT-166

GS88036AT-166 Summary of contents

Page 1

TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2 3.3 V +10%/–10% core ...

Page 2

GS88018A 100-Pin TQFP Pinout 100 DDQ ...

Page 3

GS88032A 100-Pin TQFP Pinout 100 DDQ ...

Page 4

GS88036A 100-Pin TQFP Pinout 100 DDQ ...

Page 5

TQFP Pin Description Symbol Type – – – I/O DQ – – — ...

Page 6

GS88018/32/36A Block Diagram Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only ...

Page 7

Mode Pin Functions Mode Name Burst Order Control Power Down Control Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate ...

Page 8

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 9

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ...

Page 10

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 11

Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V Voltage on Clock Input Pin CK V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin ...

Page 12

Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3 I/O Supply Voltage DDQ 2 I/O Supply Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character ...

Page 13

Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case ...

Page 14

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 15

Rev: 1.02 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36AT-250/225/200/166/150/133 15/26 © 2001, Giga Semiconductor, Inc. ...

Page 16

AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...

Page 17

Write Cycle Timing Single Write ADSP ADSC ADV – 0 WR1 – Hi-Z DQ ...

Page 18

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV – RD1 – ...

Page 19

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV – RD1 – ...

Page 20

Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV – RD1 – Hi ...

Page 21

Pipelined SCD Read-Write Cycle Timing Single Read ADSP ADSC ADV – 0 RD1 – ...

Page 22

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 23

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 24

... GS88032AT-166 256K x 32 GS88032AT-150 256K x 32 GS88032AT-133 256K x 36 GS88036AT-250 256K x 36 GS88036AT-225 256K x 36 GS88036AT-200 256K x 36 GS88036AT-166 256K x 36 GS88036AT-150 256K x 36 GS88036AT-133 512K x 18 GS88018AT-250I 512K x 18 GS88018AT-225I 512K x 18 GS88018AT-200I 512K x 18 GS88018AT-166I 512K x 18 ...

Page 25

... GS88032AT-133I 256K x 36 GS88036AT-250I 256K x 36 GS88036AT-225I 256K x 36 GS88036AT-200I 256K x 36 GS88036AT-166I 256K x 36 GS88036AT-150I 256K x 36 GS88036AT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88018AT-150IT. 2. ...

Page 26

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 88018A_r1 88018A_r1; 88018A_r1_01 88018A_r1_01; 88018A_r1_02 Rev: 1.02 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36AT-250/225/200/166/150/133 • Creation ...

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