GS8160Z18T-133 GSI Technology, GS8160Z18T-133 Datasheet

GS8160Z18T-133

Manufacturer Part Number

GS8160Z18T-133

Description

8.5ns 133MHz 1M x 18 18MB pipelined and flow through synchronous NBT SRAM

Manufacturer

GSI Technology

Datasheet

1.GS8160Z18T-133.pdf (26 pages)

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Company:

Meier Automation Equipment Co., Limited

Part Number:

GS8160Z18T-133I

Manufacturer:

GSI

Quantity:

20 000

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

Rev: 2.13a 9/2002

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Flow Through

Through

Pipeline

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

3-1-1-1

2-1-1-1

3.3 V

2.5 V

Flow

3.3 V

2.5 V

Read/Write

Pipelined

Address

Data I/O

Clock

Curr

tCycle

(x32/x36)

(x18)

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

5.5

18Mb Pipelined and Flow Through

255

300

250

295

165

190

165

190

2.7

4.4

6.0

230

270

230

265

160

180

160

180

3.0

5.0

6.5

Synchronous NBT SRAM

200

230

195

225

150

170

150

170

3.4

6.0

7.0

185

215

180

210

145

165

145

165

3.8

6.7

7.5

165

190

165

185

135

150

135

150

4.0

7.5

8.5

1/26

Functional Description

The GS8160Z18/36T is an 18Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8160Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, meaning that in addition to the rising edge

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8160Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package.

GS8160Z18/36T-250/225/200/166/150/133

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160Z18T-133

GS8160Z18T-133 Summary of contents

Page 1

Pipelined and Flow Through 100-Pin TQFP Commercial Temp Industrial Temp Features • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 ...

Page 2

... GS8160Z18T Pinout 100 DDQ DDQ DDQ V 21 ...

Page 3

GS8160Z36T Pinout 100 DDQ ...

Page 4

TQFP Pin Descriptions Symbol Type – ...

Page 5

GS8160Z18/36 NBT SRAM Functional Block Diagram Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/26 © 1998, Giga Semiconductor, Inc. ...

Page 6

Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in ...

Page 7

Synchronous Truth Table Operation Type Address Deselect Cycle, Power Down D Deselect Cycle, Power Down D Deselect Cycle, Power Down D Deselect Cycle, Continue D Read Cycle, Begin Burst R Read Cycle, Continue Burst B NOP/Read, Begin Burst R Dummy ...

Page 8

Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...

Page 9

Pipeline Mode Data I/O State Diagram Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 2.13a 9/2002 Specifications cited ...

Page 10

Flow Through Mode Data I/O State Diagram B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 2.13a 9/2002 Specifications cited are subject to ...

Page 11

Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address ...

Page 12

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 13

Absolute Maximum Ratings (All voltages reference Symbol V Voltage Voltage in V DDQ V Voltage on Clock Input Pin CK V I/O V Voltage on Other Input Pins IN I Input Current ...

Page 14

Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3 I/O Supply Voltage DDQ 2 I/O Supply Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character ...

Page 15

Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case ...

Page 16

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 17

Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS18/36-250/225/200/166/150/133 17/26 © 1998, Giga Semiconductor, Inc. ...

Page 18

AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid tKQX Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid tKQX Flow ...

Page 19

Pipeline Mode Read/Write Cycle Timing CKE ADV – – Write Write COMMAND D(A2) D(A1) ...

Page 20

Pipeline Mode No-Op, Stall and Deselect Timing CKE ADV – Write D(A1) COMMAND *Note High (False ...

Page 21

Flow Through Mode Read/Write Cycle Timing CKE ADV – D(A1 Write COMMAND D(A1) *Note High ...

Page 22

Flow Through Mode No-Op, Stall and Deselect Timing CKE ADV – Write COMMAND D(A1) *Note High (False ...

Page 23

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 24

... GS8160Z36T-150 512K x 36 GS8160Z36T-133 GS8160Z18T-250I GS8160Z18T-225I GS8160Z18T-200I GS8160Z18T-166I GS8160Z18T-150I GS8160Z18T-133I 512K x 36 GS8160Z36T-250I 512K x 36 GS8160Z36T-225I 512K x 36 GS8160Z36T-200I 512K x 36 GS8160Z36T-166I 512K x 36 GS8160Z36T-150I 512K x 36 GS8160Z36T-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816Z36-166IT. ...

Page 25

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content GS18/36 1.00 9/1999A;GS18/ 362.0012/1999B GS18/362.00 12/1999BGS18/ 362.01 1/2000C GS18/362.0 1/2000DGS18/ 362.03 2/2000E GS18/362.03 2/2000E; 8160Z18_r2_04 8160Z18_r2_04; 8160Z18_r2_05 8160Z18_r2_05; 8160Z18_r2_06 8160Z18_r2_06; 8160Z18_r2_07 8160Z18_r2_07; 8160Z18_r2_08 8160Z18_r2_08; ...

Page 26

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8160Z18_r2_10; 8160Z18_r2_11 8160Z18_r2_11; 8160Z18_r2_12 8160Z18_r2_12; 8160Z18_r2_13 Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Page;Revisions;Reason ...

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