IS61C6416-15T INTEGRATED CIRCUIT SOLUTION, IS61C6416-15T Datasheet

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IS61C6416-15T

Manufacturer Part Number
IS61C6416-15T
Description
15ns; 5V; 64K x 16 high-speed CMOS static RAM
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet

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FEATURES
• High-speed access time: 10, 12, 15, and 20 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
• Three state outputs
• Industrial temperature available
• Available in 44-pin SOJ package and
FUNCTIONAL BLOCK DIAGRAM
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR012-0B
IS61C6416
64K x 16 HIGH-SPEED CMOS STATIC RAM
— 1650 mW (max) @ -10ns Cycle
— 55 µW (max) CMOS Standby
required
44-pin TSOP-2
Lower Byte
Upper Byte
I/O8-I/O15
I/O0-I/O7
A0-A15
VCC
GND
OE
WE
CE
UB
LB
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
RAM organized as 65,536 words by 16 bits. It is fabricated
using
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 10 ns with low power
consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61C6416 is packaged in the JEDEC standard 44-pin
400mil SOJ and 44-pin 400mil TSOP-2.
ICSI
ICSI
IS61C6416 is a high-speed, 1,048,576-bit static
's high-performance CMOS technology. This highly
MEMORY ARRAY
COLUMN I/O
64K x 16
1

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IS61C6416-15T Summary of contents

Page 1

... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C6416 is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2. DECODER MEMORY ARRAY ...

Page 2

... IS61C6416 PIN CONFIGURATIONS 44-Pin SOJ A15 A14 A13 A12 A11 I/ I/O15 I/ I/O14 I/ I/O13 I/ I/O12 Vcc 11 34 GND GND 12 33 Vcc I/ I/O11 I/ I/O10 I/ I/ A10 18 27 ...

Page 3

... IS61C6416 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage ...

Page 4

... IS61C6416 CAPACITANCE (1) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time ...

Page 5

... IS61C6416 AC WAVEFORMS READ CYCLE NO. 1 (Address Controlled) ( (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...

Page 6

... IS61C6416 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width t PWE t Data Setup to Write End ...

Page 7

... IS61C6416 AC WAVEFORMS WRITE CYCLE NO Controlled) WE ADDRESS UB DATA UNDEFINED OUT D IN Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. ...

Page 8

... IS61C6416 WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ADDRESS OE CE LOW UB DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...

Page 9

... IS61C6416 WRITE CYCLE NO. 4 (UB/LB Back to Back Write) ADDRESS OE CE LOW WE UB OUT DATA UNDEFINED D IN Integrated Circuit Solution Inc. SR012- ADDRESS 1 ADDRESS PBW WORD 1 HZWE HIGH DATA IN VALID PBW WORD 2 t LZWE ...

Page 10

... SOJ 400mil TSOP-2 400mil SOJ 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. Order Part No. Package IS61C6416-12TI 400mil TSOP-2 IS61C6416-12KI 400mil SOJ IS61C6416-15TI 400mil TSOP-2 IS61C6416-15KI 400mil SOJ IS61C6416-20TI 400mil TSOP-2 IS61C6416-20KI 400mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. ...

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