GS74116ATP-12 GSI Technology, GS74116ATP-12 Datasheet

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GS74116ATP-12

Manufacturer Part Number
GS74116ATP-12
Description
Manufacturer
GSI Technology
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
GS74116ATP-12
Manufacturer:
GS
Quantity:
282
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 150/130/105/95 mA at
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
Description
The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II
packages.
Pin Descriptions
Rev: 1.03 10/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
minimum cycle time
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
DQ
Symbol
A
V
0
1
V
WE
CE
UB
OE
NC
LB
–A
–DQ
DD
SS
17
16
Lower byte enable input
Upper byte enable input
4Mb Asynchronous SRAM
+3.3 V power supply
Output enable input
Write enable input
Chip enable input
Data input/output
Description
(DQ9 to DQ16)
(DQ1 to DQ8)
Address input
No connect
Ground
256K x 16
1/14
SOJ 256K x 16-Pin Configuration (Package J)
FP-BGA 256K x 16 Bump Configuration (Package X)
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
V
A
V
WE
A
A
A
A
CE
A
A
A
A
A
DD
12
SS
15
14
13
16
4
3
2
1
0
1
2
3
4
5
8
A
B
C
D
E
G
H
F
DQ
DQ
DQ
V
DQ
V
NC
LB
DD
1
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
16
14
11
9
6 x 10 mm Bump Pitch
DQ
DQ
DQ
DQ
A
OE
UB
NC
2
12
15
13
12
10
Top view
44-pin
SOJ
A
A
A
NC
A
A
A
A
3
17
10
13
0
3
5
8
© 2001, Giga Semiconductor, Inc.
Center V
A
A
A
A
A
A
A
A
4
16
11
14
1
4
6
7
9
GS74116ATP/J/X
DQ
DQ
DQ
DQ
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
WE
27
26
25
24
23
CE
A
5
15
7, 8, 10, 12 ns
2
2
4
5
7
DD
DQ
DQ
V
DQ
DQ
V
NC
NC
DD
3.3 V V
6
SS
A
A
A
OE
UB
LB
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
5
6
7
SS
DD
8
9
10
11
1
3
6
8
17
and V
16
15
14
13
12
11
10
9
DD
SS

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GS74116ATP-12 Summary of contents

Page 1

... DQ6 DQ7 FP-BGA 256K x 16 Bump Configuration (Package X) Address input Ground No connect 1/14 GS74116ATP/J 10 Center Top view ...

Page 2

... A14 Row Memory Array Decoder Address Input Buffer Column Decoder I/O Buffer Control DQ 1 2/14 GS74116ATP/J ...

Page 3

... High Z Symbol Rating V –0.5 to +4.6 DD –0 +0 4.6 V max.) –0 +0 OUT ( 4.6 V max.) PD 0.7 T –55 to 150 STG 3/14 GS74116ATP/J Current Not Selected ISB , ISB 1 2 Read High Z Read Write I DD Not Write, High Z Write High Z High Z Unit ...

Page 4

... OUT Test Conditions Min – Output High Z – OUT – — LO 4/14 GS74116ATP/J/X Max Unit Unit Max — 0.4 V © 2001, Giga Semiconductor, Inc. ...

Page 5

... – 0. Conditions V/ns 1.4 V 1.4 V Fig. 1& 2 5/14 GS74116ATP/J/X –40 to 85° 160 140 115 100 Output Load 30pF VT = 1.4 V Output Load 2 3.3 V 589 ...

Page 6

... BLZ * — 3.5 — — 3 — t OHZ * — 3 — t BHZ , UB and Previous Data 6/14 GS74116ATP/J/X -8 -10 -12 Max Min Max Min Max — 10 — 12 — 8 — 10 — — 10 — 12 3.5 — 4 — 5 3.5 — 4 — 5 — ...

Page 7

... GS74116ATP/J/X tHZ tBHZ tOHZ Data valid -10 -12 Max Min Max Min Max — 10 — 12 — — 7 — 8 — — 7 — 8 — — 7 — 8 — — ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tCW tBW tAS tWP tDW Data valid tWHZ High impedance tWC tAW tAS tCW tBW tWP tDW tDH Data valid High impedance 8/14 GS74116ATP/J/X tWR tDH tWLZ tWR1 © 2001, Giga Semiconductor, Inc. ...

Page 9

... Write Cycle 3: UB, LB control Address Data In Data Out Rev: 1.03 10/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tAS tCW tBW tWP tDW tDH Data valid High impedance 9/14 GS74116ATP/J/X tWR1 © 2001, Giga Semiconductor, Inc. ...

Page 10

... Detail Notes: 1. Dimension D& not include interlead flash 2. Dimension B1 does not include dambar protrusion / intrusion 3. Controlling dimension: inches 10/14 GS74116ATP/J/X Dimension in inch Dimension in mm min nom max min nom — — 0.148 — — 0.025 — — 0.635 — ...

Page 11

... Detail A Notes: 1. Dimension D& not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm 11/14 GS74116ATP/J/X Dimension in inch Dimension in mm min nom max min nom max — — 0.047 — — 0.002 — — 0.05 — 0.037 ...

Page 12

... Index Rev: 1.03 10/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Top View Side View aaa Bottom View 12/14 GS74116ATP/J/X Symbol Unit 1.10±0.10 A1 0.20~0. 0.30~0.40 c 0.36(TYP) D 10.0±0.05 D1 5.25 E 6.0±0.05 E1 3.75 e ...

Page 13

... GS74116ATP-10 400 mil TSOP-II GS74116ATP-12 400 mil TSOP-II GS74116ATP-7I 400 mil TSOP-II GS74116ATP-8I 400 mil TSOP-II GS74116ATP-10I 400 mil TSOP-II GS74116ATP-12I 400 mil TSOP-II GS74116AJ-7 400 mil SOJ GS74116AJ-8 400 mil SOJ GS74116AJ-10 400 mil SOJ GS74116AJ-12 400 mil SOJ GS74116AJ-7I ...

Page 14

... Changed D3 on FPBGA pinout to A17 and • Updated Recommended Operating Conditions on page 4 Content • Updated Read Cycle and Write Cycle AC Characteristics tables • Removed 6 ns speed bin from entire document Content 14/14 GS74116ATP/J/X Page #/Revisions/Reason © 2001, Giga Semiconductor, Inc. ...

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