GS8160Z18BGT-200 GSI Technology, GS8160Z18BGT-200 Datasheet

GS8160Z18BGT-200

Manufacturer Part Number

GS8160Z18BGT-200

Description

Manufacturer

GSI Technology

Datasheet

1.GS8160Z18BGT-200.pdf (23 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

The GS8160Z18/36BT is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.00 8/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Flow Through

Pipeline

3-1-1-1

2-1-1-1

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/23

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8160Z18/36BT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

The GS8160Z18/36BT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

-250

280

330

210

240

2.5

4.0

5.5

-200

230

270

185

205

3.0

5.0

6.5

-150

185

210

170

190

3.8

6.7

7.5

GS8160Z18/36BT-250/200/150

Unit

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

Related parts for GS8160Z18BGT-200

GS8160Z18BGT-200 Summary of contents

Page 1

... KQ 4.0 5.0 tCycle 280 230 Curr (x18) 330 270 Curr (x32/x36) t 5.5 6.5 KQ 5.5 6.5 tCycle 210 185 Curr (x18) 240 205 Curr (x32/x36) 1/23 Preliminary GS8160Z18/36BT-250/200/150 250 MHz–150 MHz 3.3 V I/O -150 Unit 3.8 ns 6.7 ns 185 mA 210 mA 7.5 ns 7.5 ns 170 mA 190 mA © 2004, GSI Technology DD ...

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... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply No Connect 4/23 Preliminary ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 2004, GSI Technology ...

Page 5

... GS8160Z18/36B NBT SRAM Functional Block Diagram Rev: 1.00 8/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36BT-250/200/150 Amps Sense Drivers Write 5/23 Preliminary © 2004, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated 6/23 Preliminary GS8160Z18/36BT-250/200/150 , E and E ). Deassertion of any one of the Enable 2 3 © 2004, GSI Technology ...

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... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 8/23 Preliminary GS8160Z18/36BT-250/200/150 New Write Burst Write B D n+3 ƒ ƒ © 2004, GSI Technology ...

Page 9

... Transition and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/23 Preliminary GS8160Z18/36BT-250/200/150 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2004, GSI Technology ...

Page 10

... Pipeline and Flow Through Read Write Control State Diagram 10/23 Preliminary GS8160Z18/36BT-250/200/150 R B Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2004, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/23 Preliminary GS8160Z18/36BT-250/200/150 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

Page 12

... Rev: 1.00 8/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 12/23 Preliminary GS8160Z18/36BT-250/200/150 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 2004, GSI Technology ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/23 Preliminary GS8160Z18/36BT-250/200/150 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 14

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 14/23 Preliminary GS8160Z18/36BT-250/200/150 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2004, GSI Technology ...

Page 15

... Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 15/23 Preliminary GS8160Z18/36BT-250/200/150 50% tKC Typ. Max. Unit 30pF © 2004, GSI Technology ...

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... GSI Technology Unit ...

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... GSI Technology ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pipeline Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH tKC tKC tLZ tS tKQ D(A) D(B) D(B+1) Q(C) tOHZ 19/23 Preliminary GS8160Z18/36BT-250/200/150 Write E Read F Write G Deselect tHZ tKQX Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology D(G) ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Flow Through Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 20/23 Preliminary GS8160Z18/36BT-250/200/150 Write E Read F Write tKQX tKQ tHZ tLZ tKQX Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology D(G) ...

Page 21

... Package width and length do not include mold protrusion. Rev: 1.00 8/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/23 Preliminary GS8160Z18/36BT-250/200/150 E1 E BPR 1999.05.18 © 2004, GSI Technology ...

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... GS8160Z18BGT-150 512K x 36 GS8160Z36BGT-250 512K x 36 GS8160Z36BGT-200 512K x 36 GS8160Z36BGT-150 GS8160Z18BGT-250I GS8160Z18BGT-200I GS8160Z18BGT-150I 512K x 36 GS8160Z36BGT-250I 512K x 36 GS8160Z36BGT-200I 512K x 36 GS8160Z36BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160Z18B-200IT. ...

Page 23

... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8160ZxxB_r1 Rev: 1.00 8/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36BT-250/200/150 Page;Revisions;Reason • Creation of new datasheet 23/23 Preliminary © 2004, GSI Technology ...

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