IS61LV3216L-15TI INTEGRATED CIRCUIT SOLUTION, IS61LV3216L-15TI Datasheet

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IS61LV3216L-15TI

Manufacturer Part Number
IS61LV3216L-15TI
Description
15ns; 3.3V; 32K x 16 low voltage CMOS static RAM
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet
FEATURES
• High-speed access time: 10, 12, 15, and 20 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V + 10%, –5% power supply for 10
• Single 3.3V ± 10% power supply for 15
• Fully static operation: no clock or refresh
• Three state outputs
• Industrial temperature available
• Available in 44-pin 400mil SOJ package and
FUNCTIONAL BLOCK DIAGRAM
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR010-0B
IS61LV3216L
32K x 16 LOW VOLTAGE CMOS STATIC RAM
— 130 mW (typical) operating
— 150 µW (typical) standby
and 12 ns
and 20 ns
required
44-pin TSOP-2
Lower Byte
Upper Byte
I/O8-I/O15
I/O0-I/O7
A0-A14
VCC
GND
OE
WE
CE
UB
LB
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
organized as 32,768 words by 16 bits. It is fabricated using
ICSI
able process coupled with innovative circuit design techniques,
yields fast access times with low power consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61LV3216L is packaged in the JEDEC standard 44-pin
400mil SOJ and 44-pin 400mil TSOP-2.
ICSI
's high-performance CMOS technology. This highly reli-
IS61LV3216L is a high-speed, 512K static RAM
MEMORY ARRAY
COLUMN I/O
32K x 16
1

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IS61LV3216L-15TI Summary of contents

Page 1

... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV3216L is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2. DECODER MEMORY ARRAY ...

Page 2

... IS61LV3216L PIN CONFIGURATIONS 44-Pin SOJ A14 A13 A12 A11 I/ I/O15 I/ I/O14 I/ I/O13 I/ I/O12 Vcc 11 34 GND GND 12 33 Vcc I/ I/O11 I/ I/O10 I/ I/ A10 18 27 ...

Page 3

... IS61LV3216L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage with Respect to GND CC V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 4

... IS61LV3216L CAPACITANCE (1) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time ...

Page 5

... IS61LV3216L AC WAVEFORMS READ CYCLE NO. 1 (Address Controlled) ( (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...

Page 6

... IS61LV3216L WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width t PWE t Data Setup to Write End ...

Page 7

... IS61LV3216L AC WAVEFORMS WRITE CYCLE NO. 1 (WE WE Controlled ADDRESS CE LB (1) WRITE D IN HIGH-Z D OUT Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) ...

Page 8

... ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 12 IS61LV3216L-12TI 400mil TSOP-2 IS61LV3216L-12KI 400mil SOJ 15 IS61LV3216L-15TI 400mil TSOP-2 IS61LV3216L-15KI 400mil SOJ 20 IS61LV3216L-20TI 400mil TSOP-2 IS61LV3216L-20KI 400mil SOJ Integrated Circuit Solution Inc. HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO ...

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