IC61C256AH-12J INTEGRATED CIRCUIT SOLUTION, IC61C256AH-12J Datasheet
IC61C256AH-12J
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IC61C256AH-12J Summary of contents
Page 1
... IC61C256AH Document Title 32K x 8 High Speed SRAM Revision History Revision No History 0A Initial Draft 0B Revise typo Add SOP package type 0D Revise typo of sop size at page 2,9 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products ...
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... Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC61C256AH is pin compatible with other 32k x 8 SRAMs and are available in 28-pin 300mil PDIP, 300mil SOJ, and 8*13.4mm TSOP-1 package, 330 mil SOP. ...
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... IC61C256AH PIN CONFIGURATION 28-Pin DIP and SOJ and SOP A14 1 28 VCC A12 A13 A11 A10 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input ...
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... IC61C256AH OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Notes preliminary. DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL (1) V Input HIGH Voltage IH (2) V Input LOW Voltage IL I Input Leakage ...
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... IC61C256AH READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACE OE Access Time t DOE OE to Low-Z Output t (2) LZOE OE to High-Z Output t (2) HZOE CE to Low-Z Output t (2) LZCE CE to High-Z Output ...
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... IC61C256AH AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions OHA ...
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... IC61C256AH WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold HA from Write End t Address Setup Time SA WE Pulse Width t (4) PWE t Data Setup to Write End SD t Data Hold from Write End ...
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... IC61C256AH WRITE CYCLE NO. 2 (CE Controlled) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ ...
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... NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, Integrated Circuit Solution Inc. AHSR010-0D 4/19/2002 ORDERING INFORMATION: IC61C256AH Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 12 IC61C256AH-12NI 300mil DIP 12 IC61C256AH-12JI 300mil SOJ 12 IC61C256AH-12TI 8*13.4mm TSOP-1 12 IC61C256AH-12UI 330mil SOP 15 IC61C256AH-15NI 300mil DIP 15 IC61C256AH-15JI 300mil SOJ ...