IS61SP6464-100PQ INTEGRATED CIRCUIT SOLUTION, IS61SP6464-100PQ Datasheet

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IS61SP6464-100PQ

Manufacturer Part Number
IS61SP6464-100PQ
Description
100MHz; 5ns; 3.3V; 64K x 64 synchronous pipelined static RAM
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet

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Part Number:
IS61SP6464-100PQ
Manufacturer:
ISSI
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Part Number:
IS61SP6464-100PQ
Manufacturer:
XILINX
0
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• Fast access time:
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control
• Five chip enables for simple depth expansion
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin LQFP and PQFP 14mm x
• Single +3.3V power supply
• Control pins mode upon power-up:
Integrated Circuit Solution Inc.
SSR009-0B
IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
– 133, 117, 100 MHz; 6 ns (83 MHz);
control
using MODE input
and address pipelining
20mm package
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or V
7 ns (75 MHz); 8 ns (66 MHz)
CCQ
to alter their power-up state
Q
DESCRIPTION
The
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the i486™, Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 65,536
words by 64 bits, fabricated with
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con-
trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-
I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GND
selects LINEAR Burst. A V
selects INTERLEAVED Burst.
ICSI
IS61SP6464 is a high-speed, low-power synchro-
CCQ
(or no connect) on MODE pin
ICSI
's advanced CMOS
Q
, on MODE pin
1

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IS61SP6464-100PQ Summary of contents

Page 1

... Processor) or ADSC (Address Status Cache Controller) input Q pins. Subsequent burst addresses can be generated internally by the IS61SP6464 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state ...

Page 2

... IS61SP6464 BLOCK DIAGRAM CLK ADV ADSC ADSP 16 A15-A0 GW BWE BW8 BW1 CE CE2 CE2 CE3 CE3 OE 2 MODE A0’ Q0 CLK A0 BINARY COUNTER A1’ CLR ADDRESS REGISTER CE CLK DQ57-DQ64 BYTE WRITE REGISTERS CLK D Q DQ8-DQ1 BYTE WRITE REGISTERS CLK ...

Page 3

... IS61SP6464 PIN CONFIGURATION 128-Pin LQFP and PQFP GNDQ 1 I I I VCCQ GNDQ I I VCCQ 25 GNDQ 26 I I ...

Page 4

... IS61SP6464 TRUTH TABLE ADDRESS OPERATION USED Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst ...

Page 5

... IS61SP6464 ASYNCHRONOUS TRUTH TABLE Operation Pipelined Read Pipelined Read Write Write Deselect Sleep WRITE TRUTH TABLE Operation Read H Read H Write all bytes H Write all bytes L Write Byte 1 H Write Byte 2 H Write Byte 3 H Write Byte 4 H Write Byte 5 ...

Page 6

... IS61SP6464 LINEAR BURST ADDRESS TABLE A1’, A0’ = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative to GND for I/O Pins IN OUT V Voltage Relative to GND for IN for Address and Control Inputs ...

Page 7

... IS61SP6464 DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current LO CAPACITANCE (1,2) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. ...

Page 8

... IS61SP6464 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I AC Operating Device Selected, CC Supply Current All Inputs = Cycle Time > Standby Current Device Deselected TTL Inputs V = Max., CC All Inputs = V CLK Cycle Time > Standby Current Device Deselected CMOS Inputs V = Max ...

Page 9

... IS61SP6464 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 10

... IS61SP6464 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 11

... IS61SP6464 READ CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 BWE BW8-BW1 t t CES CEH CES CEH CE2, CE3 t t CES CEH CE2, CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA ...

Page 12

... IS61SP6464 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time CES t Address Advance Setup Time ...

Page 13

... IS61SP6464 WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A15-A0 WR1 BWE t WS BW8-BW1 WR1 t t CES CEH CES CEH CE2, CE3 t t CES CEH CE2, CE3 OE High-Z ...

Page 14

... IS61SP6464 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 15

... IS61SP6464 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 16

... IS61SP6464 READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 BWE BW8-BW1 t t CES CEH CES CEH CE2, CE3 t t CES CEH CE2, CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA ...

Page 17

... IS61SP6464 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (3) t Clock High to Output Invalid KQX (3,4) t Clock High to Output Low-Z KQLZ (3,4) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 18

... IS61SP6464 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (3) t Clock High to Output Invalid KQX (3,4) t Clock High to Output Low-Z KQLZ (3,4) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 19

... IS61SP6464 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 GW BWE BW8-BW1 t t CES CEH CES CEH CE2, CE3 t t CES CEH CE2, CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA ...

Page 20

... NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, 20 Order Part Number 133 IS61SP6464-133TQ 14*20*1.4mm LQFP IS61SP6464-133PQ 14*20*2.7mm PQFP 117 IS61SP6464-117TQ 14*20*1.4mm LQFP IS61SP6464-117PQ 14*20*2.7mm PQFP 100 IS61SP6464-100TQ 14*20*1.4mm LQFP IS61SP6464-100PQ 14*20*2.7mm PQFP 83 IS61SP6464-6TQ IS61SP6464-6PQ 75 IS61SP6464-7TQ IS61SP6464-7PQ 66 IS61SP6464-8TQ IS61SP6464-8PQ 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. ...

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