GS84036T-100I GSI Technology, GS84036T-100I Datasheet

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GS84036T-100I

Manufacturer Part Number
GS84036T-100I
Description
100MHz 12ns 128K x 36 4Mb sync NBT SRAM
Manufacturer
GSI Technology
Datasheet
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.
Functional Description
Applications
The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version)
high performance synchronous SRAM with a 2 bit burst address
counter. Although of a type originally developed for Level 2 Cache
applications supporting high performance CPU’s, the device now
finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support. The GS84018/32/36
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA
package.
Controls
Addresses, data I/O’s, chip enables (E
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
Rev: 2.05 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Flow Through
Pipeline
3-1-1-1
2-1-1-1
tCycle
tCycle
t
I
t
I
KQ
DD
KQ
DD
330mA
190mA
5.5ns
3.2ns
10ns
-180
8ns
256K x 18, 128K x 32, 128K x 36
1
, E
310mA
190mA
6.0ns
3.5ns
8.5ns
10ns
-166
2
, E
3
4Mb Sync Burst SRAMs
), address burst control
275mA
190mA
6.6ns
3.8ns
10ns
10ns
-150
190mA
140mA
4.5ns
10ns
12ns
15ns
-100
1/31
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the
BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
SCD Pipelined Reads
The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available.SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS84018/32/36 operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (V
pins are used to de-couple output noise from the internal circuit.
GS84018/32/36T/B-180/166/150/100
© 1999, Giga Semiconductor, Inc.
180Mhz - 100Mhz
3.3V & 2.5V I/O
3.3V VDD
DDQ
)

Related parts for GS84036T-100I

GS84036T-100I Summary of contents

Page 1

TQFP, BGA Commercial Temp Industrial Temp Features • FT pin for user configurable flow through or pipelined operation. • Single Cycle Deselect (SCD) Operation. • 3.3V +10%/-5% Core power supply • ...

Page 2

GS84018 100 Pin TQFP Pinout 100 DDQ ...

Page 3

GS84032 100 Pin TQFP Pinout 100 DDQ ...

Page 4

GS84036 100 Pin TQFP Pinout 100 DDQ ...

Page 5

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78 ...

Page 6

GS84018 Pad Out Rev: 2.05 6/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119 Bump BGA - ...

Page 7

GS84032 Pad Out Rev: 2.05 6/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119 Bump BGA - ...

Page 8

GS84036Pad Out Rev: 2.05 6/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119 Bump BGA - Top ...

Page 9

BGA Pin Description Pin Location N4, P4 A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, R2, R6, T3 T2, T6 T2, T6 K7, K6, L7, L6, M6, N7, N6 H7, H6, G7, G6, F6, ...

Page 10

GS84018/32/36 Block Diagram Register A0- LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version ...

Page 11

Mode Pin Functions Mode Name Pin Name State Burst Order Control Output Register Control Power Down Control Note: There are pull up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input ...

Page 12

Synchronous Truth Table Operation Address Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 13

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E and that ADSP is ...

Page 14

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 15

Absolute Maximum Ratings ) (All voltages reference Symbol Description V Voltage on V Pins Voltage in V Pins DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V ...

Page 16

Undershoot Measurement and Timing 50% V -2.0V SS 20% tKC Capacitance o (T =25 C, f=1MH , V =3.3V Parameter Control Input Capacitance Input Capacitance Output Capacitance Note: This parameter is sample tested. ...

Page 17

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 18

Operating Currents Parameter Test Conditions Symbol Device Selected; Operating Pipeline All other inputs Current Flow-Thru Output open Standby Pipeline 0.2V DD Current Flow-Thru Device Deselected; Deselect Pipeline All other inputs Current V ...

Page 19

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- Thru Clock to Output Invalid Clock to Output in Low-Z Clock ...

Page 20

Write Cycle Timing Single Write ADSP ADSC ADV -An 0 WR1 Hi ...

Page 21

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV -An RD1 tOLZ ...

Page 22

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0-An RD1 tOE G tKQ Hi-Z ...

Page 23

Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV RD1 Hi ...

Page 24

Pipelined SCD Read - Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0-An RD1 Hi-Z ...

Page 25

Sleep Mode Timing Diagram ADSP ADSC ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers ...

Page 26

GS 84018/32/36 Output Driver Characteristics 60 Pull Down Drivers -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 3. Rev: 2.05 6/2000 Specifications cited are subject to change without notice. For latest documentation see ...

Page 27

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 28

Package Dimensions - 119 Pin BGA A Pin 1 Corner P N Top View Side View Rev: 2.05 6/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Bottom View ...

Page 29

... GS84032T-166I 128K x 32 GS84032T-150I 128K x 32 GS84032T-100I 128K x 36 GS84036T-180I 128K x 36 GS84036T-166I 128K x 36 GS84036T-150I 128K x 36 GS84036T-100I 256K x 18 GS84018B-180 256K x 18 GS84018B-166 256K x 18 GS84018B-150 256K x 18 GS84018B-100 128K x 32 GS84032B-180 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T. ...

Page 30

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings. Rev: 2.05 6/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ...

Page 31

Revision History Types of Changes Rev. Code: Old; Format or Content New GS84018/32/36 Rev 1.02c 5/1999; GS84018/32/36 2.00 8/1999D GS84018/32/362.00 8/ 1999;GS84018/32/362.01 9/1999E GS84018/32/362.01 9/ 1999E;GS84018/32/362.02 GS84018/32/362.0210-11/ 1999;GS84018/32/362.032/2000G GS84018/32/362.032/2000G; GS84018_r2_04 84018_r2_04; 84018_r2_05 Rev: 2.05 6/2000 Specifications cited are subject to ...

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