GS71024T-12 GSI Technology, GS71024T-12 Datasheet

no-image

GS71024T-12

Manufacturer Part Number
GS71024T-12
Description
12ns 64K x 24 1.5Mb asynchronous SRAM
Manufacturer
GSI Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GS71024T-12
Manufacturer:
GSI
Quantity:
20 000
Part Number:
GS71024T-12I
Manufacturer:
GSI
Quantity:
1 000
Part Number:
GS71024T-12I
Manufacturer:
GSI
Quantity:
20 000
Part Number:
GS71024T-12IT
Manufacturer:
GS
Quantity:
20 000
TQFP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 8, 9, 10, 12, 15 ns
• CMOS low power operation: 190/170/160/130/110 mA at
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
Description
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
Pin Descriptions
Rev: 1.05 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
minimum cycle time.
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
GT: Pb-Free 100-pin TQFP available
CE1, CE2
Symbol
A
0
V
WE
to A
X/Y
DD
15
CE1
CE2
A14
A15
X/Y
V/S
WE
OE
A0
0
1
+3.3 V power supply
Write enable input
Chip enable input
Description
1.5Mb Asynchronous SRAM
Address input
Q
Vector Input
Address
Control
Input
1/13
Block Diagram
64K x 24
Decoder
Row
DQ
Symbol
1
V/S
V
OE
to DQ
Fine Pitch BGA Bump Configuration
SS
A
B
C
D
E
G
H
F
6 mm x 8 mm, 0.75 mm Bump Pitch
24
DQ1
V
V
Memory Array
DQ
DQ
DQ
DQ
DQ
DQ
1024 x 1536
1
SS
DD
I/O Buffer
Column
Decoder
A
DQ
DQ
DQ
DQ
DQ
DQ
A
2
15
3
DQ24
Top View
CE2
CE1
A
A
Address Multiplexer Control
A
A
A
A
3
11
14
2
5
7
9
Output enable input
Data input/output
Description
WE
A
A
OE
A
A
A
A
4
10
13
1
4
6
8
Ground
Center V
© 1999, GSI Technology
DQ
DQ
DQ
DQ
DQ
DQ
A
8, 9, 10, 12, 15 ns
A
5
12
0
GS71024T/U
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DD
6
DD
SS
3.3 V V
and V
DD
SS

Related parts for GS71024T-12

GS71024T-12 Summary of contents

Page 1

... Asynchronous SRAM Description Symbol Address input Vector Input V/S Write enable input OE Chip enable input V Block Diagram Row Decoder Address Input Q Control 1/13 GS71024T 10, 12 Center V Fine Pitch BGA Bump Configuration ...

Page 2

... Rev: 1.05 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 100-Pin TQFP Pinout Top View 2/13 GS71024T ...

Page 3

... Write using A15 Data In X Output disable High Z Symbol Rating V –0.5 to +4.6 DD –0 0 (≤ 4.6 V max.) –0 0 OUT (≤ 4.6 V max –55 to 150 STG 3/13 GS71024T/U V Current DD ISB1, ISB2 I DD Unit © 1999, GSI Technology ...

Page 4

... OUT OUT Test Conditions Output High OUT –4mA +4mA OL OL 4/13 GS71024T/U Typical Maximum 3.3 3.6 3.3 3 0.3 — DD — 0.8 — 70 — 85 Maximum = Minimum Maximum –1uA –1uA 2.4 — © 1999, GSI Technology Unit ...

Page 5

... V 190 mA 170 mA 160 mA 130 mA 110 mA 165 mA 135 mA 115 ≤ – 0 5/13 GS71024T/U Output Load 1 DQ 30pF 50Ω 1.4 V Output Load 2 3.3 V 589Ω 434Ω 5pF -40 to 85° ...

Page 6

... OLZ * t — 4 — 4 — 4 — 4.5 t OHZ Read Cycle Previous Data t OH1 t AV 6/13 GS71024T/U -10 -12 -15 Min Max Min Max Min Max 10 — 12 — 15 — — 10 — 12 — 15 — 10 — 12 — 15 — 10 — 12 — 15 — ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Read Cycle OLZ High impedance *1 CE1 represents both CE1 low and CE2 high. 7/13 GS71024T OHZ Data valid © 1999, GSI Technology ...

Page 8

... — 0 — — 0 — — 0 — WR1 * t 2 — 2.5 — WLZ * — 4 — 4.5 t WHZ 8/13 GS71024T/U -10 -12 -15 Min Max Min Max Min Max 10 — 12 — 15 — 7 — 8 — 10 — 7 — 8 — 10 — 7 — 8 — 10 — 5 — 6 — ...

Page 9

... WP t WHZ (*3) Write Cycle 2: CE control High impedance *1 CE1 represents both CE1 low and CE2 high. 9/13 GS71024T (* Data valid t WLZ High impedance (*3) t WR1 Data valid © 1999, GSI Technology ...

Page 10

... Rev: 1.05 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Fine Pitch BGA 0.10 ± 8.00 5.25 10/13 GS71024T/U 0.10 © 1999, GSI Technology ...

Page 11

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion Rev: 1.05 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. TQFP Package Drawing θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 22.0 22.1 20.0 20.1 e 16.0 16.1 14.0 14.1 0.65 b 0.60 0.75 1.00 0.10 7° 11/13 GS71024T BPR 1999.05.18 © 1999, GSI Technology ...

Page 12

... GS71024T-10 100-Pin TQFP GS71024T-12 100-Pin TQFP GS71024T-15 100-Pin TQFP GS71024T-8I 100-Pin TQFP GS71024T-9I 100-Pin TQFP GS71024T-10I 100-Pin TQFP GS71024T-12I 100-Pin TQFP GS71024T-15I 100-Pin TQFP GS71024GT-8 Pb-free 100-Pin TQFP GS71024GT-9 Pb-free 100-Pin TQFP GS71024GT-10 Pb-free 100-Pin TQFP GS71024GT-12 Pb-free 100-Pin TQFP GS71024GT-15 ...

Page 13

... Package GS71024U-12I Fine Pitch BGA GS71024U-15I Fine Pitch BGA * Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS71024T/U-12T. Revision History Rev. Code: Old; New GS71024Rev 2:17pm, 4/8/ 1999 ...

Related keywords