IS61SF6432-10TQ INTEGRATED CIRCUIT SOLUTION, IS61SF6432-10TQ Datasheet

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IS61SF6432-10TQ

Manufacturer Part Number
IS61SF6432-10TQ
Description
10ns; 3.3V; 64K x 32 synchronous flow-through static RAM
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet

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Part Number:
IS61SF6432-10TQI
Manufacturer:
ISSI
Quantity:
20 000
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
IS61SF6432
Integrated Circuit Solution Inc.
SSR004-0B
IS61SF6432
64K x 32 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
FEATURES
• Fast access time: 9 ns, 10 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin LQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
• Control pins mode upon power-up:
• Industrial temperature available
control
using MODE input
and address pipelining
eliminate multiple bank bus contention.
– FT in pipeline mode
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or V
CCQ
to alter their power-up state
Q
DESCRIPTION
The
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SF6432 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
(or no connect) on MODE pin selects INTERLEAVED Burst.
ICSI
IS61SF6432 is a high-speed, low-power synchro-
Q
, on MODE pin selects LINEAR Burst. A V
ICSI
's advanced CMOS technology.
CCQ
1

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IS61SF6432-10TQ Summary of contents

Page 1

... Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SF6432 and controlled by the ADV (burst address Q advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE) ...

Page 2

... IS61SF6432 BLOCK DIAGRAM CLK ADV ADSC ADSP 16 A15-A0 GW BWE BW4 BW3 BW2 BW1 CE1 CE2 CE3 OE 2 MODE A0’ CLK BINARY COUNTER A1’ CLR ADDRESS REGISTER CE CLK DQ32-DQ25 BYTE WRITE REGISTERS CLK D Q DQ24-DQ17 BYTE WRITE ...

Page 3

... IS61SF6432 PIN CONFIGURATION 100-Pin LQFP and PQFP (Top View) 100 DQ17 3 DQ18 4 VCCQ 5 GNDQ 6 DQ19 7 DQ20 8 DQ21 9 DQ22 10 GNDQ 11 VCCQ 12 DQ23 13 DQ24 GNDQ 14 VCC GND 18 DQ25 19 DQ26 20 VCCQ ...

Page 4

... IS61SF6432 TRUTH TABLE ADDRESS OPERATION USED Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External ...

Page 5

... IS61SF6432 INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = GND A1’, A0’ = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) ...

Page 6

... IS61SF6432 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current ...

Page 7

... IS61SF6432 CAPACITANCE (1,2) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 8

... IS61SF6432 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (2) t Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z KQHZ t Address Setup Time AS t Address Status Setup Time ...

Page 9

... IS61SF6432 READ CYCLE TIMING: FLOW-THROUGH CLK ADSP ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read Flow-through Integrated Circuit Solution Inc ...

Page 10

... IS61SF6432 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time CES t Address Advance Setup Time ...

Page 11

... IS61SF6432 WRITE CYCLE TIMING: PIPELINE CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A15-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 OE High-Z ...

Page 12

... IS61SF6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (2) t Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z KQHZ (2) t Output Disable to Output Invalid ...

Page 13

... IS61SF6432 READ/WRITE CYCLE TIMING: FLOW-THROUGH CLK ADSP ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read Flow-through Integrated Circuit Solution Inc ...

Page 14

... IS61SF6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (4) t Clock High to Output Invalid KQX (4,5) t Clock High to Output Low-Z KQLZ (4,5) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 15

... IS61SF6432 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 GW BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN ZZ Single Read Integrated Circuit Solution Inc ...

Page 16

... IS61SF6432-9TQ 14*20*1.4mm LQFP IS61SF6432-9PQ 14*20*2.7mm PQFP IS61SF6432-10TQ 14*20*1.4mm LQFP IS61SF6432-10PQ 14*20*2.7mm PQFP Order Part Number Package IS61SF6432-10TQI 14*20*1.4mm LQFP IS61SF6432-10PQI 14*20*2.7mm PQFP Integrated Circuit Solution Inc. 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 ...

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