IS61SP12832-166TQ INTEGRATED CIRCUIT SOLUTION, IS61SP12832-166TQ Datasheet

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IS61SP12832-166TQ

Manufacturer Part Number
IS61SP12832-166TQ
Description
166MHz; 3.3V; 128K x 32 synchoronous pipelined static RAM
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• JEDEC 100-Pin LQFP and
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
FAST ACCESS TIME
Integrated Circuit Solution Inc.
SSR011-0B
IS61SP12832
128K x 32 SYNCHRONOUS
PIPELINED STATIC RAM
control
using MODE input
and address pipelining
119-pin PBGA package
Symbol
t
t
KQ
KC
Parameter
Clock Access Time
Cycle Time
Frenquency
-166
166
3.5
6
DESCRIPTION
The
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 131,072
words by 32 bits, fabricated with
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,
BW4 controls DQd, conditioned by BWE being LOW. A LOW
on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP12832 and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
-150
150
3.8
6.7
ICSI
IS61SP12832 is a high-speed, low-power synchro-
-133
133
7.5
4
-117
117
8.5
4
ICSI
's advanced CMOS
100
10
-5
5
Units
MHz
ns
ns
1

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IS61SP12832-166TQ Summary of contents

Page 1

... Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP12832 and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW ...

Page 2

... IS61SP12832 BLOCK DIAGRAM CLK ADV ADSC ADSP 17 A16-A0 GW BWE BW4 BW3 BW2 BW1 CE CE2 CE2 OE 2 MODE A0’ Q0 CLK A0 BINARY COUNTER A1’ CLR ADDRESS REGISTER CE CLK DQd BYTE WRITE REGISTERS CLK D Q DQc BYTE WRITE REGISTERS CLK ...

Page 3

... IS61SP12832 PIN CONFIGURATION 119-pin PBGA (Top View) and 100-Pin LQFP VCCQ A6 A4 ADSP CE2 A3 ADSC VCC A12 D DQc1 NC GND NC GND E DQc2 DQc3 GND CE GND F VCCQ DQc4 GND OE GND G DQc5 DQc6 BW3 ADV BW2 H DQc7 DQc8 GND ...

Page 4

... IS61SP12832 TRUTH TABLE Address Operation Used Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Next ...

Page 5

... IS61SP12832 INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = GND A1’, A0’ = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) ...

Page 6

... IS61SP12832 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current ...

Page 7

... IS61SP12832 CAPACITANCE (1,2) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 8

... IS61SP12832 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter f Clock Frequency MAX t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 9

... IS61SP12832 READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN Single Read Integrated Circuit Solution Inc ...

Page 10

... IS61SP12832 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time CES t Address Advance Setup Time ...

Page 11

... IS61SP12832 WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A16-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT ...

Page 12

... IS61SP12832 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 13

... IS61SP12832 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A16-A0 RD1 GW BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN ZZ Single Read Integrated Circuit Solution Inc ...

Page 14

... Commercial Range: 0°C to +70°C Speed 166 MHz 150 MHz 133 MHz 117 MHz 5 ns NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, 14 Order Part Number Package IS61SP12832-166TQ 14x20x1.4mm LQFP IS61SP12832-166B 14*22mm PBGA IS61SP12832-150TQ 14*20*1.4mm LQFP IS61SP12832-150B 14*22mm PBGA IS61SP12832-133TQ 14*20*1.4mm LQFP IS61SP12832-133B 14*22mm PBGA IS61SP12832-117TQ 14*20*1 ...

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