IC61LV25616-15T INTEGRATED CIRCUIT SOLUTION, IC61LV25616-15T Datasheet
IC61LV25616-15T
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IC61LV25616-15T Summary of contents
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... IC61LV25616 Document Title 256K x 16 Hight Speed SRAM with 3.3V Revision History Revision No History 0A Initial Draft The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...
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... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC61LV25616 is packaged in the JEDEC standard 44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TF- BGA. DECODER ...
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... IC61LV25616 PIN CONFIGURATIONS 44-Pin TSOP-2 and SOJ I/O0 7 I/O1 8 I/O2 9 I/O3 10 Vcc 11 GND 12 I/O4 13 I/O5 14 I/ PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input ...
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... IC61LV25616 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS V Vcc Related to GND CC T Storage Temperature STG P Power Dissipation T OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS ...
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... IC61LV25616 CAPACITANCE (1) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time ...
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... IC61LV25616 AC WAVEFORMS READ CYCLE NO. 1 (1,2) (Address Controlled) ( ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...
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... IC61LV25616 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width t PWE t Data Setup to Write End ...
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... IC61LV25616 AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled HIGH or LOW) ADDRESS UB DATA UNDEFINED OUT D IN Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. ...
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... IC61LV25616 AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CE LOW UB OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN Integrated Circuit Solution Inc. ...
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... IC61LV25616 AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ADDRESS OE CE LOW WE UB OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The referenced to the rising or falling edge of the signal that terminates the Write ...
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... TSOP-2 IC61LV25616-10KI 400mil SOJ IC61LV25616-10BI 6*8mm TF-BGA IC61LV25616-12TI 400mil TSOP-2 IC61LV25616-12KI 400mil SOJ IC61LV25616-12BI 6*8mm TF-BGA IC61LV25616-15TI 400mil TSOP-2 IC61LV25616-15KI 400mil SOJ IC61LV25616-15BI 6*8mm TF-BGA Integrated Circuit Solution Inc. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: ...