24C16-S ETC-unknow, 24C16-S Datasheet
24C16-S
Available stocks
Related parts for 24C16-S
24C16-S Summary of contents
Page 1
Standard EEPROM ICs SLx 24C08/16 8/16 Kbit (1024/2048 Serial CMOS-EEPROM with 2 C Synchronous 2-Wire Bus I Data Sheet 1998-07-27 8 bit) ...
Page 2
SLx 24C08/16 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version Text was changed to “Typical programming time 5 ms for bytes” ...
Page 3
Kbit (1024/2048 2 EEPROMs Synchronous 2-Wire Bus Features • Data EEPROM internally organized as 1024/2048 bytes and 64/128 pages • Low power CMOS V • = 2.7 to 5.5 V operation CC • Two wire serial interface ...
Page 4
... Q67100-H3226 SLE 24C08-S Q67100-H3227 SLA 24C16-D Q67100-H3513 SLA 24C16-S Q67100-H3508 SLA 24C16-D-3 Q67100-H3512 SLA 24C16-S-3 Q67100-H3507 SLE 24C16-D Q67100-H3229 SLE 24C16-S Q67100-H3230 Other types are available on request – Temperature range (– 55 °C – Package (die, wafer delivery) 1 Pin Configuration P-DIP-8 ...
Page 5
Pin Definitions and Functions Table 1 Pin No. Symbol SDA 6 SCL Pin Description Serial Clock (SCL) The SCL input is used to clock data into ...
Page 6
Description The SLx 24C08/16 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 1024/2048 64/128 pages. The 16 bytes of a page can be programmed simultaneously. The device conforms to the specification of the ...
Page 7
C-Bus Characteristics I The SLx 24C08/16 devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave. SCL Master SDA Figure 3 Bus Configuration Master Device that initiates the transfer ...
Page 8
The conventions for the serial clock line and the bidirectional data line are shown in figure 4. SCL 1 SDA START Condition Figure 4 2 C-Bus Timing Conventions for START Condition, STOP Condition, Data Valida- I tion and Transfer of ...
Page 9
Device Addressing and EEPROM Addressing After a START condition, the master always transmits a Command Byte CSW or CSR. After the acknowledge of the EEPROM a Control Byte follows, its content and the transmitter depend on the previous Command ...
Page 10
The timing conventions for read and write operations are described in figures 5 and 6. Command Byte (CSW) SCL SDA START from Master Figure 5 Timing of the Command Byte CSW Command Byte (CSR) ...
Page 11
Write Operations Changing of the EEPROM data is initiated by the master with the command byte CSW. Depending on the state of the Write Protection pin WP either one byte (Byte Write bytes (Page Write) ...
Page 12
Page Write Address Setting Transmission of Data Programming Cycle Those bytes of the page that have not been addressed are not included in the programming Bus Activity Command Byte R Master CSW T SDA Line S ...
Page 13
Acknowledge Polling During the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed. At the end of active programming the chip returns to the standby mode and the last ...
Page 14
STOP from Master initiates erase/write cycle START from Master CSR SDA STOP from Master initiates erase/write cycle START from Master CSW SDA Figure 10 Principle of Acknowledge Polling Semiconductor Group CSR ...
Page 15
Read Operations Reading of the EEPROM data is initiated by the Master with the command byte CSR. 6.1 Random Read Random read operations allow the master to access any memory location. Address Setting Transmission of CSR Transmission of EEPROM ...
Page 16
Current Address Read The EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the Master has served an ...
Page 17
Sequential Read A sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM then continues the data transmission. The ...
Page 18
Electrical Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at voltage. 7.1 Absolute Maximum Ratings Stresses ...
Page 19
DC Characteristics (cont’d) Parameter Symbol V Input high IH voltage Output low V OL voltage C Input/output I/O capacitance (SDA) C Input IN capacitance (other pins) C Capacitive load b for each bus line 1) The values for I ...
Page 20
AC Characteristics Parameter SCL clock frequency Clock pulse width low Clock pulse width high SDA and SCL rise time SDA and SCL fall time Start set-up time Start hold time Data in set-up time Data in hold time SCL ...
Page 21
SCL t SU.STA t HD.STA SDA In Start Condition SDA Out Figure 14 Bus Timing Data Semiconductor Group LOW HIGH t SU.DAT t HD.DAT SLx 24C08/ SU.STO ...
Page 22
Package Outlines P-DIP-8-4 (Plastic Dual In-line Package) P-DSO-8-3 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 22 SLx ...