VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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Power Management Events
Three types of power management events are supported:
1) ACPI-required Fixed Events defined in the PM1a_STS
and PM1a_EN registers. These events can trigger either
SCI or SMI depending on the SCI_EN bit:
• PWRBTN# Triggering
• RTC Alarm
• Sleep Button
• ACPI Power Management Timer Carry (always SCI)
• BIOS Release (always SCI)
2) ACPI-aware General Purpose Function Events defined
in the GP_STS and GP_SCI_EN, and GP_SMI_EN
registers. These events can trigger either SCI or SMI
depending on the setting of individual SMI and SCI
enable bits:
• External SMI triggering
• USB Resume
• Ring Indicator (RI#)
• Battery Low Detect (BATLOW#)
• Notebook Lid Open/Close Detect (LID)
• Thermal Detect (THRM#)
GCLK
3D
Graphics
Controller
PCKRUN#
PCI Bus
PCLK
BIOS ROM
Keyboard / Mouse
Figure 7. System Block Diagram Using the VT82C686B Super South Bridge
Revision 1.71 June 9, 2000
3) Generic Global Events defined in the GBL_STS and
System and Processor Resume Events
Depending on the system suspend state, different features can
be enabled to resume the system. There are two classes of
resume events:
a)
b)
Host CPU
SMIACT#
VT82C598
AGP Bus
(Apollo MVP3)
GCKRUN#
or
VT82C693
(Apollo ProPlus)
SUSCLK,
SUSST1#
ISA
VT82C686A
IDE
Super South
USB
-119-
GBL_EN registers. These registers are mainly used for
SMI:
• PCI Bus Clock Run Resume
• Primary Interrupt Occurance
• GP0 and GP1 Timer Time Out
• Secondary Event Timer Time Out
• Occurrence of Primary Events
(defined in register PACT_STS and PACT_EN)
• Legacy USB accesses (keyboard and mouse)
- Software SMI
VCCS-based events.
Event logic resides in the
VCCS plane and thus can resume the system from
any suspend state. Such events include PWRBTN#,
RI#, BATLOW#, LID, SMBus resume event, RTC
alarm, EXTSMI#, and GP1 (EXTSMI1#).
VCC-Based Events. Event logic resides in the VCC
plane and thus can only resume the system from the
POS state. Such events include the ACPI PM timer,
USB resume, and EXTSMIn#.
HCLK
SMI# / STPCLK#
CPU Bus
L2 Cache
(Socket-7 Only)
FPG, EDO, or
Memory Bus
SDRAM
CKE#
(SDR or DDR)
HCLK
GCLK
PCLK
Module ID
MCLK
SMBus
CPUSTP#
Clock
PCISTP#
Generator
GPIO and ACPI Events
Power Plane & Peripheral Control
Functional Descriptions
VT82C686B